From: fangyu.yu@linux.alibaba.com
To: joro@8bytes.org, will@kernel.org, robin.murphy@arm.com,
pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu,
alex@ghiti.fr, tjeznach@rivosinc.com, jgg@ziepe.ca,
kevin.tian@intel.com, baolu.lu@linux.intel.com,
vasant.hegde@amd.com, anup@brainfault.org, atish.patra@linux.dev,
skhawaja@google.com, jgg@nvidia.com, nutty.liu@hotmail.com
Cc: guoren@kernel.org, andrew.jones@oss.qualcomm.com,
kvm@vger.kernel.org, iommu@lists.linux.dev,
kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org,
Fangyu Yu <fangyu.yu@linux.alibaba.com>
Subject: [PATCH v4 0/2] iommu/riscv: Support Svpbmt memory types in generic_pt
Date: Tue, 12 May 2026 15:41:40 +0800 [thread overview]
Message-ID: <20260512074142.16356-1-fangyu.yu@linux.alibaba.com> (raw)
From: Fangyu Yu <fangyu.yu@linux.alibaba.com>
RISC-V Svpbmt adds page-based memory types (PBMT) to PTEs, allowing
mappings to be tagged as e.g. normal memory, non-cacheable memory, or
I/O.
This series wires the RISC-V IOMMU Svpbmt capability into generic_pt
and uses PBMT to encode device memory attributes for IOMMU mappings.
---
Changes in v4:
- Fix build warning on 32-bit configurations by using BIT_ULL() for RISCVPT_NC and RISCVPT_IO.
- Link to v3:
https://lore.kernel.org/linux-riscv/20260417140746.97817-1-fangyu.yu@linux.alibaba.com/
---
Changes in v3:
- Include RISCVPT_NC and RISCVPT_IO in riscvpt_attr_from_entry()
so iommupt KUnit tests preserve these descriptor bits..
- Link to v2:
https://lore.kernel.org/linux-riscv/20260414110212.79526-1-fangyu.yu@linux.alibaba.com
---
Changes in v2:
- Add a comment for PT_FEAT_RISCV_SVPBMT (per Kevin and Jason).
- Clarify PBMT encoding condition, sort PBMT-related bits by
position, and drop the redundant PBMT clear(per Kevin).
- Link to v1:
https://lore.kernel.org/linux-iommu/20260411022223.91029-1-fangyu.yu@linux.alibaba.com/
Fangyu Yu (2):
iommu/riscv: Advertise Svpbmt support to generic page table
iommupt: Encode IOMMU_MMIO/IOMMU_CACHE via RISC-V Svpbmt bits
drivers/iommu/generic_pt/fmt/riscv.h | 11 ++++++++++-
drivers/iommu/riscv/iommu.c | 2 ++
include/linux/generic_pt/common.h | 4 ++++
3 files changed, 16 insertions(+), 1 deletion(-)
--
2.50.1
--
kvm-riscv mailing list
kvm-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/kvm-riscv
WARNING: multiple messages have this Message-ID (diff)
From: fangyu.yu@linux.alibaba.com
To: joro@8bytes.org, will@kernel.org, robin.murphy@arm.com,
pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu,
alex@ghiti.fr, tjeznach@rivosinc.com, jgg@ziepe.ca,
kevin.tian@intel.com, baolu.lu@linux.intel.com,
vasant.hegde@amd.com, anup@brainfault.org, atish.patra@linux.dev,
skhawaja@google.com, jgg@nvidia.com, nutty.liu@hotmail.com
Cc: guoren@kernel.org, andrew.jones@oss.qualcomm.com,
kvm@vger.kernel.org, iommu@lists.linux.dev,
kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org,
Fangyu Yu <fangyu.yu@linux.alibaba.com>
Subject: [PATCH v4 0/2] iommu/riscv: Support Svpbmt memory types in generic_pt
Date: Tue, 12 May 2026 15:41:40 +0800 [thread overview]
Message-ID: <20260512074142.16356-1-fangyu.yu@linux.alibaba.com> (raw)
From: Fangyu Yu <fangyu.yu@linux.alibaba.com>
RISC-V Svpbmt adds page-based memory types (PBMT) to PTEs, allowing
mappings to be tagged as e.g. normal memory, non-cacheable memory, or
I/O.
This series wires the RISC-V IOMMU Svpbmt capability into generic_pt
and uses PBMT to encode device memory attributes for IOMMU mappings.
---
Changes in v4:
- Fix build warning on 32-bit configurations by using BIT_ULL() for RISCVPT_NC and RISCVPT_IO.
- Link to v3:
https://lore.kernel.org/linux-riscv/20260417140746.97817-1-fangyu.yu@linux.alibaba.com/
---
Changes in v3:
- Include RISCVPT_NC and RISCVPT_IO in riscvpt_attr_from_entry()
so iommupt KUnit tests preserve these descriptor bits..
- Link to v2:
https://lore.kernel.org/linux-riscv/20260414110212.79526-1-fangyu.yu@linux.alibaba.com
---
Changes in v2:
- Add a comment for PT_FEAT_RISCV_SVPBMT (per Kevin and Jason).
- Clarify PBMT encoding condition, sort PBMT-related bits by
position, and drop the redundant PBMT clear(per Kevin).
- Link to v1:
https://lore.kernel.org/linux-iommu/20260411022223.91029-1-fangyu.yu@linux.alibaba.com/
Fangyu Yu (2):
iommu/riscv: Advertise Svpbmt support to generic page table
iommupt: Encode IOMMU_MMIO/IOMMU_CACHE via RISC-V Svpbmt bits
drivers/iommu/generic_pt/fmt/riscv.h | 11 ++++++++++-
drivers/iommu/riscv/iommu.c | 2 ++
include/linux/generic_pt/common.h | 4 ++++
3 files changed, 16 insertions(+), 1 deletion(-)
--
2.50.1
WARNING: multiple messages have this Message-ID (diff)
From: fangyu.yu@linux.alibaba.com
To: joro@8bytes.org, will@kernel.org, robin.murphy@arm.com,
pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu,
alex@ghiti.fr, tjeznach@rivosinc.com, jgg@ziepe.ca,
kevin.tian@intel.com, baolu.lu@linux.intel.com,
vasant.hegde@amd.com, anup@brainfault.org, atish.patra@linux.dev,
skhawaja@google.com, jgg@nvidia.com, nutty.liu@hotmail.com
Cc: guoren@kernel.org, andrew.jones@oss.qualcomm.com,
kvm@vger.kernel.org, iommu@lists.linux.dev,
kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org,
Fangyu Yu <fangyu.yu@linux.alibaba.com>
Subject: [PATCH v4 0/2] iommu/riscv: Support Svpbmt memory types in generic_pt
Date: Tue, 12 May 2026 15:41:40 +0800 [thread overview]
Message-ID: <20260512074142.16356-1-fangyu.yu@linux.alibaba.com> (raw)
From: Fangyu Yu <fangyu.yu@linux.alibaba.com>
RISC-V Svpbmt adds page-based memory types (PBMT) to PTEs, allowing
mappings to be tagged as e.g. normal memory, non-cacheable memory, or
I/O.
This series wires the RISC-V IOMMU Svpbmt capability into generic_pt
and uses PBMT to encode device memory attributes for IOMMU mappings.
---
Changes in v4:
- Fix build warning on 32-bit configurations by using BIT_ULL() for RISCVPT_NC and RISCVPT_IO.
- Link to v3:
https://lore.kernel.org/linux-riscv/20260417140746.97817-1-fangyu.yu@linux.alibaba.com/
---
Changes in v3:
- Include RISCVPT_NC and RISCVPT_IO in riscvpt_attr_from_entry()
so iommupt KUnit tests preserve these descriptor bits..
- Link to v2:
https://lore.kernel.org/linux-riscv/20260414110212.79526-1-fangyu.yu@linux.alibaba.com
---
Changes in v2:
- Add a comment for PT_FEAT_RISCV_SVPBMT (per Kevin and Jason).
- Clarify PBMT encoding condition, sort PBMT-related bits by
position, and drop the redundant PBMT clear(per Kevin).
- Link to v1:
https://lore.kernel.org/linux-iommu/20260411022223.91029-1-fangyu.yu@linux.alibaba.com/
Fangyu Yu (2):
iommu/riscv: Advertise Svpbmt support to generic page table
iommupt: Encode IOMMU_MMIO/IOMMU_CACHE via RISC-V Svpbmt bits
drivers/iommu/generic_pt/fmt/riscv.h | 11 ++++++++++-
drivers/iommu/riscv/iommu.c | 2 ++
include/linux/generic_pt/common.h | 4 ++++
3 files changed, 16 insertions(+), 1 deletion(-)
--
2.50.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
next reply other threads:[~2026-05-12 7:42 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-12 7:41 fangyu.yu [this message]
2026-05-12 7:41 ` [PATCH v4 0/2] iommu/riscv: Support Svpbmt memory types in generic_pt fangyu.yu
2026-05-12 7:41 ` fangyu.yu
2026-05-12 7:41 ` [PATCH v4 1/2] iommu/riscv: Advertise Svpbmt support to generic page table fangyu.yu
2026-05-12 7:41 ` fangyu.yu
2026-05-12 7:41 ` fangyu.yu
2026-05-12 7:41 ` [PATCH v4 2/2] iommupt: Encode IOMMU_MMIO/IOMMU_CACHE via RISC-V Svpbmt bits fangyu.yu
2026-05-12 7:41 ` fangyu.yu
2026-05-12 7:41 ` fangyu.yu
2026-05-12 13:34 ` [PATCH v4 0/2] iommu/riscv: Support Svpbmt memory types in generic_pt Jörg Rödel
2026-05-12 13:34 ` Jörg Rödel
2026-05-12 13:34 ` Jörg Rödel
2026-05-12 14:50 ` fangyu.yu
2026-05-12 14:50 ` fangyu.yu
2026-05-12 14:50 ` fangyu.yu
2026-06-26 8:21 ` patchwork-bot+linux-riscv
2026-06-26 8:21 ` patchwork-bot+linux-riscv
2026-06-26 8:21 ` patchwork-bot+linux-riscv
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