Re: [PATCH v2 2/2] perf: RISC-V: store available counter mask as bitmap - patchwork-bot+linux-riscv

From: patchwork-bot+linux-riscv@kernel.org
To: Xixin Liu <liuxixin@kylinos.cn>
Cc: linux-riscv@lists.infradead.org, atish.patra@linux.dev,
	anup@brainfault.org, will@kernel.org, mark.rutland@arm.com,
	pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu,
	alex@ghiti.fr, linux-arm-kernel@lists.infradead.org,
	linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 2/2] perf: RISC-V: store available counter mask as bitmap
Date: Tue, 01 Sep 2026 01:20:09 +0000	[thread overview]
Message-ID: <178822560914.869454.14196508746211130249.git-patchwork-notify@kernel.org> (raw)
In-Reply-To: <prpmask02cmap.v2.1786434000.git.liuxixin@kylinos.cn>

Hello:

This series was applied to riscv/linux.git (fixes)
by Paul Walmsley <pjw@kernel.org>:

On Tue, 18 Aug 2026 17:10:00 +0800 you wrote:
> The available-counter mask was a single unsigned long, but iteration
> uses RISCV_MAX_COUNTERS, which is 64. On RV32 that reads past the object.
> Filling with an unsigned-long bit at index 32 and above is also wrong.
> 
> Use DECLARE_BITMAP and set_bit/bitmap helpers. Walk each bitmap word
> into CFG_MATCH when checking events, when allocating an index, and when
> stopping all counters. Set the counter base to i times BITS_PER_LONG.
> Share the CFG_MATCH ecall through a small helper so the 32-bit argument
> split is not duplicated. On qemu-system-riscv32 the probe bitmap has bits
> above XLEN set, so the first word alone is not enough.
> 
> [...]

Here is the summary with links:
  - [v2,2/2] perf: RISC-V: store available counter mask as bitmap
    https://git.kernel.org/riscv/c/e7bdbf5131ff
  - [v2,1/2] perf: RISC-V: use BIT_ULL for u64 overflow masks
    (no matching commit)

You are awesome, thank you!
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