patches for SGI O2

patches for SGI O2

[Vivien Chappelier]

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Hi,

	I've a few patches for running Linux on the SGI O2:

The first one (O2-asid) concerns the TLB initialization the IP32. The
asid_cache is not initialized, which leads to MMU context = 0 being
considered valid! Thus when switching task, in switch_mm, a new context is
not created. With the patch I can boot a debian experimental system (from
ftp://bolugftp.uni-bonn.de/pub/mips-linux/rootfs/experimental)

The second one adds support for the 16550A UARTs of the O2, so that ARC
console is not needed anymore.

Finaly, with my configuration (SGI O2 R5000 @ 180Mhz) I've to change
PAGE_OFFSET in page.h to the one used for IP22 rather than the one used
for IP32.. here is a third patch (O2-page) to change this, but I'm not
sure about other configurations (R10000?)

regards,
Vivien.


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diff -Naur linux/arch/mips64/sgi-ip32/ip32-setup.c linux.patch/arch/mips64/sgi-ip32/ip32-setup.c
--- linux/arch/mips64/sgi-ip32/ip32-setup.c	Sun Dec  9 15:47:15 2001
+++ linux.patch/arch/mips64/sgi-ip32/ip32-setup.c	Sat Dec 15 22:56:29 2001
@@ -58,6 +58,7 @@
 #ifdef CONFIG_SERIAL_CONSOLE
 	char *ctype;
 #endif
+	current_cpu_data.asid_cache = ASID_FIRST_VERSION;
 	TLBMISS_HANDLER_SETUP ();
 
 #ifdef CONFIG_SERIAL_CONSOLE

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diff -Naur linux/arch/mips64/arc/arc_con.c linux.patch/arch/mips64/arc/arc_con.c
--- linux/arch/mips64/arc/arc_con.c	Sun Dec  9 15:47:10 2001
+++ linux.patch/arch/mips64/arc/arc_con.c	Mon Dec 10 20:35:44 2001
@@ -15,14 +15,7 @@
 #include <asm/sgialib.h>
 
 extern void prom_printf (char *, ...);
-
-void prom_putchar(char c)
-{
-	ULONG cnt;
-	CHAR it = c;
-
-	ArcWrite(1, &it, 1, &cnt);
-}
+extern void prom_putchar(char c);
 
 static void prom_console_write(struct console *co, const char *s,
 			       unsigned count)
diff -Naur linux/arch/mips64/arc/console.c linux.patch/arch/mips64/arc/console.c
--- linux/arch/mips64/arc/console.c	Sun Dec  9 15:47:10 2001
+++ linux.patch/arch/mips64/arc/console.c	Mon Dec 10 20:35:34 2001
@@ -11,6 +11,14 @@
 
 static char ppbuf[1024];
 
+void prom_putchar(char c)
+{
+	ULONG cnt;
+	CHAR it = c;
+
+	ArcWrite(1, &it, 1, &cnt);
+}
+
 void prom_printf(char *fmt, ...)
 {
 	va_list args;
diff -Naur linux/include/asm-mips64/serial.h linux.patch/include/asm-mips64/serial.h
--- linux/include/asm-mips64/serial.h	Sun Dec  9 15:52:28 2001
+++ linux.patch/include/asm-mips64/serial.h	Mon Dec 10 20:35:08 2001
@@ -18,6 +18,8 @@
  */
 #define BASE_BAUD (1843200 / 16)
 
+#if defined(CONFIG_SGI_IP27)
+
 /*
  * Note about serial ports and consoles:
  * For console output, everyone uses the IOC3 UARTA (offset 0x178)
@@ -49,5 +51,40 @@
 #define RS_TABLE_SIZE	64
 
 #define SERIAL_PORT_DFNS
+
+#elif defined(CONFIG_SGI_IP32)
+
+#include <asm/ip32/ip32_ints.h>
+
+/*
+ * The IP32 (SGI O2) has standard serial ports (UART 16550A) mapped in memory
+ */
+
+#define RS_TABLE_SIZE
+
+/* Standard COM flags (except for COM4, because of the 8514 problem) */
+#ifdef CONFIG_SERIAL_DETECT_IRQ
+#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST | ASYNC_AUTO_IRQ)
+#define STD_COM4_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_AUTO_IRQ)
+#else
+#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF/* | ASYNC_SKIP_TEST*/)
+#define STD_COM4_FLAGS ASYNC_BOOT_AUTOCONF
+#endif
+
+#define SERIAL_PORT_DFNS				\
+        { baud_base: BASE_BAUD,				\
+	  irq: MACEISA_SERIAL1_IRQ,			\
+          flags: STD_COM_FLAGS,				\
+          iomem_base: (u8*)MACE_BASE+MACEISA_SER1_BASE,	\
+          iomem_reg_shift: 8,				\
+          io_type: SERIAL_IO_MEM},                      \
+        { baud_base: BASE_BAUD,				\
+	  irq: MACEISA_SERIAL2_IRQ,			\
+          flags: STD_COM_FLAGS,				\
+          iomem_base: (u8*)MACE_BASE+MACEISA_SER2_BASE,	\
+          iomem_reg_shift: 8,				\
+          io_type: SERIAL_IO_MEM},                      
+#endif
+
 
 #endif /* _ASM_SERIAL_H */

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diff -Naur linux/include/asm-mips64/page.h linux.patch/include/asm-mips64/page.h
--- linux/include/asm-mips64/page.h	Sat Dec 15 21:33:40 2001
+++ linux.patch/include/asm-mips64/page.h	Sat Dec 15 21:37:38 2001
@@ -60,10 +60,10 @@
  * at XKPHYS for kernels with more than that.
  */
 #if defined(CONFIG_SGI_IP22) || defined(CONFIG_MIPS_ATLAS) || \
-    defined(CONFIG_MIPS_MALTA)
+    defined(CONFIG_MIPS_MALTA) || defined(CONFIG_SGI_IP32)
 #define PAGE_OFFSET	0xffffffff80000000UL
 #endif
-#if defined(CONFIG_SGI_IP27) || defined(CONFIG_SGI_IP32)
+#if defined(CONFIG_SGI_IP27)
 #define PAGE_OFFSET	0xa800000000000000UL
 #endif
 

Re: patches for SGI O2

[Ralf Baechle]

On Sat, Dec 15, 2001 at 11:52:58PM +0100, Vivien Chappelier wrote:

> The first one (O2-asid) concerns the TLB initialization the IP32. The
> asid_cache is not initialized, which leads to MMU context = 0 being
> considered valid! Thus when switching task, in switch_mm, a new context is
> not created.

Correct finding.  It's just that you shouldn't have to apply this patch
to the IP32 code and that shows that mips64 needs quite a cleanup there.
Applied anyway.

> Finaly, with my configuration (SGI O2 R5000 @ 180Mhz) I've to change
> PAGE_OFFSET in page.h to the one used for IP22 rather than the one used
> for IP32.. here is a third patch (O2-page) to change this, but I'm not
> sure about other configurations (R10000?)

> -#if defined(CONFIG_SGI_IP27) || defined(CONFIG_SGI_IP32)
> +#if defined(CONFIG_SGI_IP27)
>  #define PAGE_OFFSET	0xa800000000000000UL
>  #endif

0xa8 is caching mode 5 which is not defined for the R5000, thus undefined
behaviour.  You can be almost certain that the CPU use that as an
excuse in order to do really funny things.

As the O2 is a non-cachecoherent machine this should also be correct for
the R10000 / R12000.

  Ralf