L1_CACHE_SHIFT value for P4 ?

L1_CACHE_SHIFT value for P4 ?

[Margit Schubert-While]

What should be the value of L1_CACHE_SHIFT for a P4 ?
L1_CACHE_BYTES is set to 1<<L1_CACHE_SHIFT

In the .config , I notice that L1_CACHE_SHIFT is being set to 7 for the P4.
Surely that can't be right or ?

Re: L1_CACHE_SHIFT value for P4 ?

[Andi Kleen]

Margit Schubert-While <margit@margit.com> writes:

E> What should be the value of L1_CACHE_SHIFT for a P4 ?
> L1_CACHE_BYTES is set to 1<<L1_CACHE_SHIFT
> 
> In the .config , I notice that L1_CACHE_SHIFT is being set to 7 for the P4.
> Surely that can't be right or ?

The P4 has 128byte L2 cache lines (2^7). The L1 apparently has smaller lines.

For practical reasons the L1_CACHE_BYTES defines should not be smaller than
the L2 line size - otherwise slab's cache colouring would not be very 
effective. In fact the symbol is a bit misnamed, it refers to all CPU caches.
So it needs to be 7.


-Andi

Re: L1_CACHE_SHIFT value for P4 ?

[Dave Jones]

On Thu, Nov 21, 2002 at 02:10:02PM +0100, Andi Kleen wrote:

 > The P4 has 128byte L2 cache lines (2^7). The L1 apparently has smaller lines.

Not mine:

L2 unified cache:
	Size: 512KB	Sectored, 8-way associative.
	line size=64 bytes.

Someone (Manfred?) pointed out a chapter in the P4 system programmer guide about
this last time I brought it up. I forget the reasoning, I'll see if I can dig it out..

		Dave

-- 
| Dave Jones.        http://www.codemonkey.org.uk
| SuSE Labs

L1_CACHE_SHIFT value for P4 ?

[Margit Schubert-While]

Andi,
L2 cache lines = L2 cache size ?
This P4 has got 512KB L2 cache.

processor         : 0
vendor_id          : GenuineIntel
cpu family          : 15
model                : 2
model name      : Intel(R) Pentium(R) 4 CPU 2.40GHz
stepping            : 4
cpu MHz            : 2400.143
cache size         : 512 KB
fdiv_bug            : no
hlt_bug              : no
f00f_bug           : no
coma_bug        : no
fpu                     : yes
fpu_exception   : yes
cpuid level         : 2
wp                      : yes
flags                  : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr 
pge mca cmov pat pse36
                             clflush dts acpi mmx fxsr sse sse2 ss ht tm
bogomips         : 4784.12

Re: L1_CACHE_SHIFT value for P4 ?

[Dave Jones]

On Thu, Nov 21, 2002 at 02:25:54PM +0100, Margit Schubert-While wrote:
 > Andi,
 > L2 cache lines = L2 cache size ?

No.

 > This P4 has got 512KB L2 cache.

That 512KB is divided into 'lines' of n bytes.
Where n is the L1_CACHE_SHIFT value. (Or should be).
x86info will tell you the line size. (Its also printk'd at boot up iirc)

		Dave

-- 
| Dave Jones.        http://www.codemonkey.org.uk
| SuSE Labs

Re: L1_CACHE_SHIFT value for P4 ?

[Andi Kleen]

On Thu, Nov 21, 2002 at 01:23:02PM +0000, Dave Jones wrote:
> On Thu, Nov 21, 2002 at 02:10:02PM +0100, Andi Kleen wrote:
> 
>  > The P4 has 128byte L2 cache lines (2^7). The L1 apparently has smaller lines.
> 
> Not mine:
> 
> L2 unified cache:
> 	Size: 512KB	Sectored, 8-way associative.
> 	line size=64 bytes.
> 
> Someone (Manfred?) pointed out a chapter in the P4 system programmer guide about
> this last time I brought it up. I forget the reasoning, I'll see if I can dig it out..

The only reference I was able to find was in the Intel Technology Journal,
which says the L2 cache has a 128 byte cache line.

http://developer.intel.com/technology/itj/q12001/articles/art_2.htm
-> "Netburst microarchitecture" -> Level 2 Instruction and Data Cache
"The L2 cache is organized as an 8-way set-associative cache with 128 bytes 
per cache line. These 128-byte cache lines consist of two 64-byte sectors. 
A miss in the L2 cache typically initiates two 64-byte access requests to the 
system bus to fill both halves of the cache line. The L2 cache is a write-back 
cache that allocates new cache lines on load or store misses. "

It is refering to the older 256K cached P4, but I doubt they changed it.
Your cache reporting may refer to the 64byte sectors or is just wrong
(would not be the first time that has happened - some P4 versions also
misreported their TLB size) 

For cache colouring purposes you need to use the 128 byte unit.

-Andi

-Andi
> 
> 		Dave
> 
> -- 
> | Dave Jones.        http://www.codemonkey.org.uk
> | SuSE Labs

Re: L1_CACHE_SHIFT value for P4 ?

[Dave Jones]

On Thu, Nov 21, 2002 at 02:42:50PM +0100, Andi Kleen wrote:

 > http://developer.intel.com/technology/itj/q12001/articles/art_2.htm
 > -> "Netburst microarchitecture" -> Level 2 Instruction and Data Cache
 > "The L2 cache is organized as an 8-way set-associative cache with 128 bytes 
 > per cache line. These 128-byte cache lines consist of two 64-byte sectors. 
 > A miss in the L2 cache typically initiates two 64-byte access requests to the 
 > system bus to fill both halves of the cache line.

Ok, this makes more sense. (and sounds familiar -- probably the same
thing I was pointed to last time this came up)
 
 > It is refering to the older 256K cached P4, but I doubt they changed it.
 > Your cache reporting may refer to the 64byte sectors or is just wrong

I think its counting just the sector. It certainly makes sense.

 > (would not be the first time that has happened - some P4 versions also
 > misreported their TLB size) 

Interesting. I should go read the errata so x86info handles that correctly..

 > For cache colouring purposes you need to use the 128 byte unit.

Agreed.

		Dave

-- 
| Dave Jones.        http://www.codemonkey.org.uk
| SuSE Labs

L1_CACHE_SHIFT value for P4 ?

[Margit Schubert-While]

Just for the record - my x86info

Instruction TLB: 4K, 2MB or 4MB pages, fully associative, 64 entries.
Data TLB: 4KB or 4MB pages, fully associative, 64 entries.
L1 Data cache:
         Size: 8KB       Sectored, 4-way associative.
         line size=64 bytes.
No L3 cache
Instruction trace cache:
         Size: 12K uOps  8-way associative.
L2 unified cache:
         Size: 512KB     Sectored, 8-way associative.
         line size=64 bytes.

Re: L1_CACHE_SHIFT value for P4 ?

[Mikael Pettersson]

Dave Jones writes:
 > On Thu, Nov 21, 2002 at 02:10:02PM +0100, Andi Kleen wrote:
 > 
 >  > The P4 has 128byte L2 cache lines (2^7). The L1 apparently has smaller lines.
 > 
 > Not mine:
 > 
 > L2 unified cache:
 > 	Size: 512KB	Sectored, 8-way associative.
 > 	line size=64 bytes.
 > 
 > Someone (Manfred?) pointed out a chapter in the P4 system programmer guide about
 > this last time I brought it up. I forget the reasoning, I'll see if I can dig it out..

The info is in the P4 Code Optimization manual. I don't have it handy,
but as I recall, the P4s have 64 byte sectors and read two sectors on
a read miss. I don't know what happens on writes.

/Mikael