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From: Greg KH <greg@kroah.com>
To: Ivan Kokshaysky <ink@jurassic.park.msu.ru>
Cc: David Brownell <david-b@pacbell.net>,
	Jeff Garzik <jgarzik@pobox.com>,
	Russell King <rmk@arm.linux.org.uk>,
	Linus Torvalds <torvalds@transmeta.com>,
	linux-kernel@vger.kernel.org
Subject: Re: [patch 2.5] PCI MWI cacheline size fix
Date: Thu, 20 Mar 2003 14:26:11 -0800	[thread overview]
Message-ID: <20030320222611.GC4607@kroah.com> (raw)
In-Reply-To: <20030320135950.A2333@jurassic.park.msu.ru>

On Thu, Mar 20, 2003 at 01:59:50PM +0300, Ivan Kokshaysky wrote:
> This is rather conservative variant of previous patch:
> - no changes required for drivers or architectures with HAVE_ARCH_PCI_MWI;
> - do respect BIOS settings: if the cacheline size is multiple
>   of that we have expected, assume that this is on purpose;
> - assume cacheline size of 32 bytes for all x86s except K7/K8 and P4.
>   Actually it's good for 386/486s as quite a few PCI devices do not support
>   smaller values.
> 
> If you all are fine with it, I can make a 2.4 counterpart.

This looks fine to me.

thanks,

greg k-h

      parent reply	other threads:[~2003-03-20 22:14 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2003-03-20 10:59 [patch 2.5] PCI MWI cacheline size fix Ivan Kokshaysky
2003-03-20 11:55 ` Dave Jones
2003-03-20 12:29   ` Ivan Kokshaysky
2003-03-20 12:54     ` Dave Jones
2003-03-20 14:33 ` Jeff Garzik
2003-03-20 15:29 ` David Brownell
2003-03-20 22:26 ` Greg KH [this message]

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