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From: David Brownell <david-b@pacbell.net>
To: Ivan Kokshaysky <ink@jurassic.park.msu.ru>
Cc: Jeff Garzik <jgarzik@pobox.com>, Greg KH <greg@kroah.com>,
	Russell King <rmk@arm.linux.org.uk>,
	Linus Torvalds <torvalds@transmeta.com>,
	linux-kernel@vger.kernel.org
Subject: Re: [patch 2.5] PCI MWI cacheline size fix
Date: Thu, 20 Mar 2003 07:29:52 -0800	[thread overview]
Message-ID: <3E79DE70.4050303@pacbell.net> (raw)
In-Reply-To: 20030320135950.A2333@jurassic.park.msu.ru

Ivan Kokshaysky wrote:
> This is rather conservative variant of previous patch:

Looks ok, and the previous patch behaved fine on the hardware
I could test it with.  The changes being: to set the cacheline
size only on the "prep_mwi" path (vs much earlier), and allow
cacheline size to be a multiple of the "real" one.


> - assume cacheline size of 32 bytes for all x86s except K7/K8 and P4.
>   Actually it's good for 386/486s as quite a few PCI devices do not support
>   smaller values.

Given the number of people that questioned that K7/K8/P4 logic,
I'd suggest putting that comment into the pcibios_init() code.


> If you all are fine with it, I can make a 2.4 counterpart.

Yes, having that avoid compile-time config is also important.

Thanks for updating this stuff -- it'll be good to know more
drivers can reduce their PCI/cache overheads.

- Dave


  parent reply	other threads:[~2003-03-20 15:12 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2003-03-20 10:59 [patch 2.5] PCI MWI cacheline size fix Ivan Kokshaysky
2003-03-20 11:55 ` Dave Jones
2003-03-20 12:29   ` Ivan Kokshaysky
2003-03-20 12:54     ` Dave Jones
2003-03-20 14:33 ` Jeff Garzik
2003-03-20 15:29 ` David Brownell [this message]
2003-03-20 22:26 ` Greg KH

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