cpufreq/linux/arch/arm/mach-sa1100 cpu-sa1100.c, 1.4, 1.5 cpu-sa1110.c, 1.10, 1.11

cpufreq/linux/arch/arm/mach-sa1100 cpu-sa1100.c, 1.4, 1.5 cpu-sa1110.c, 1.10, 1.11

[Ducrot Bruno]

Update of /mnt/src/cvsroot/cpufreq/linux/arch/arm/mach-sa1100
In directory flint:/tmp/cvs-serv2114/linux/arch/arm/mach-sa1100

Modified Files:
	cpu-sa1100.c cpu-sa1110.c 
Log Message:
Merge with davej cpufreq bk tree.

Index: cpu-sa1100.c
===================================================================
RCS file: /mnt/src/cvsroot/cpufreq/linux/arch/arm/mach-sa1100/cpu-sa1100.c,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -r1.4 -r1.5
--- cpu-sa1100.c	19 Aug 2003 13:38:31 -0000	1.4
+++ cpu-sa1100.c	5 Nov 2003 18:27:41 -0000	1.5
@@ -194,7 +194,7 @@
 		new_ppcr = sa11x0_freq_to_ppcr(target_freq);
 		if ((sa11x0_ppcr_to_freq(new_ppcr) > target_freq) &&
 		    (sa11x0_ppcr_to_freq(new_ppcr - 1) >= policy->min))
-			mew_ppcr--;
+			new_ppcr--;
 		break;
 	}
 
@@ -222,7 +222,7 @@
 	if (policy->cpu != 0)
 		return -EINVAL;
 	policy->cur = policy->min = policy->max = sa11x0_getspeed();
-	policy->policy = CPUFREQ_POLICY_POWERSAVE;
+	policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
 	policy->cpuinfo.min_freq = 59000;
 	policy->cpuinfo.max_freq = 287000;
 	policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;

Index: cpu-sa1110.c
===================================================================
RCS file: /mnt/src/cvsroot/cpufreq/linux/arch/arm/mach-sa1100/cpu-sa1110.c,v
retrieving revision 1.10
retrieving revision 1.11
diff -u -r1.10 -r1.11
--- cpu-sa1110.c	19 Aug 2003 13:38:32 -0000	1.10
+++ cpu-sa1110.c	5 Nov 2003 18:27:41 -0000	1.11
@@ -270,8 +270,12 @@
 	 * We wait 20ms to be safe.
 	 */
 	sdram_set_refresh(2);
+	if (!irqs_disabled()) {
 	set_current_state(TASK_UNINTERRUPTIBLE);
 	schedule_timeout(20 * HZ / 1000);
+	} else {
+		mdelay(20);
+	}
 
 	/*
 	 * Reprogram the DRAM timings with interrupts disabled, and
@@ -282,19 +286,19 @@
 	local_irq_save(flags);
 	asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
 	udelay(10);
-	__asm__ __volatile__("
-		b	2f
-		.align	5
-1:		str	%3, [%1, #0]		@ MDCNFG
-		str	%4, [%1, #28]		@ MDREFR
-		str	%5, [%1, #4]		@ MDCAS0
-		str	%6, [%1, #8]		@ MDCAS1
-		str	%7, [%1, #12]		@ MDCAS2
-		str	%8, [%2, #0]		@ PPCR
-		ldr	%0, [%1, #0]
-		b	3f
-2:		b	1b
-3:		nop
+	__asm__ __volatile__("					\n\
+		b	2f					\n\
+		.align	5					\n\
+1:		str	%3, [%1, #0]		@ MDCNFG	\n\
+		str	%4, [%1, #28]		@ MDREFR	\n\
+		str	%5, [%1, #4]		@ MDCAS0	\n\
+		str	%6, [%1, #8]		@ MDCAS1	\n\
+		str	%7, [%1, #12]		@ MDCAS2	\n\
+		str	%8, [%2, #0]		@ PPCR		\n\
+		ldr	%0, [%1, #0]				\n\
+		b	3f					\n\
+2:		b	1b					\n\
+3:		nop						\n\
 		nop"
 		: "=&r" (unused)
 		: "r" (&MDCNFG), "r" (&PPCR), "0" (sd.mdcnfg),
@@ -317,7 +321,7 @@
 	if (policy->cpu != 0)
 		return -EINVAL;
 	policy->cur = policy->min = policy->max = sa11x0_getspeed();
-	policy->policy = CPUFREQ_POLICY_POWERSAVE;
+	policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
 	policy->cpuinfo.min_freq = 59000;
 	policy->cpuinfo.max_freq = 287000;
 	policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;

Re: cpufreq/linux/arch/arm/mach-sa1100 cpu-sa1100.c, 1.4, 1.5 cpu-sa1110.c, 1.10, 1.11

[Russell King]

On Wed, Nov 05, 2003 at 06:28:14PM +0000, Ducrot Bruno wrote:
> --- cpu-sa1110.c	19 Aug 2003 13:38:32 -0000	1.10
> +++ cpu-sa1110.c	5 Nov 2003 18:27:41 -0000	1.11
> @@ -270,8 +270,12 @@
>  	 * We wait 20ms to be safe.
>  	 */
>  	sdram_set_refresh(2);
> +	if (!irqs_disabled()) {
>  	set_current_state(TASK_UNINTERRUPTIBLE);
>  	schedule_timeout(20 * HZ / 1000);
> +	} else {
> +		mdelay(20);
> +	}

Hmm, this doesn't look right.  Did you apply a patch generated by ignoring
space changes, 'cause this doesn't reflect what is actually in Linus tree,
which is:

	if (!irqs_disabled()) {
		set_current_state(TASK_UNINTERRUPTIBLE);
		schedule_timeout(20 * HZ / 1000);
	} else {
		mdelay(20);
	}


-- 
Russell King
 Linux kernel    2.6 ARM Linux   - http://www.arm.linux.org.uk/
 maintainer of:  2.6 PCMCIA      - http://pcmcia.arm.linux.org.uk/
                 2.6 Serial core