From: Andi Kleen <ak@suse.de>
To: Grant Grundler <iod00d@hp.com>
Cc: netdev@vger.kernel.org, openib-general@openib.org
Subject: Re: Timeline of IPoIB performance
Date: Tue, 11 Oct 2005 02:51:22 +0200 [thread overview]
Message-ID: <200510110251.22442.ak@suse.de> (raw)
In-Reply-To: <20051010233054.GA11213@esmail.cup.hp.com>
On Tuesday 11 October 2005 01:30, Grant Grundler wrote:
> On Mon, Oct 10, 2005 at 02:26:52PM -0700, Grant Grundler wrote:
> ...
>
> > If it's interleaving, every other cacheline will be "local".
>
> ISTR AMD64 was page-interleaved but then got confused by documents
> describing "128-bit" 2-way interleave. I now realize the 128bit
> is refering to interleave between two "banks" of memory behind
> each memory controller. ie 2 * 128-bit provides in the 32-byte
> cacheline size that most x86 programs expect.
The cache line size on K7 and K8 is 64 bytes.
> Anyway, I'm hoping that we'll see a consistent result if node interleave
> is turned off.
Yes usually a good idea.
-Andi
next prev parent reply other threads:[~2005-10-11 0:51 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <1128672413.13948.326.camel@localhost>
[not found] ` <52br20lsei.fsf@cisco.com>
2005-10-08 2:25 ` Timeline of IPoIB performance Matt Leininger
2005-10-10 18:23 ` Roland Dreier
2005-10-10 20:03 ` Michael S. Tsirkin
2005-10-10 21:03 ` Roland Dreier
2005-10-10 20:17 ` Rick Jones
2005-10-10 20:58 ` Roland Dreier
2005-10-10 21:22 ` Rick Jones
2005-10-10 21:26 ` Grant Grundler
2005-10-10 23:30 ` Grant Grundler
2005-10-11 0:51 ` Andi Kleen [this message]
2005-10-10 23:25 ` Matt Leininger
2005-10-10 23:38 ` Roland Dreier
2005-10-10 23:44 ` Matt Leininger
2005-10-10 23:53 ` Roland Dreier
2005-10-11 4:03 ` Roland Dreier
[not found] <E1EPIxF-0001Cp-00@gondolin.me.apana.org.au>
2005-10-12 16:53 ` Roland Dreier
2005-10-12 18:28 ` Matt Leininger
2005-10-13 1:24 ` Matt Leininger
2005-10-13 1:48 ` Herbert Xu
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