Re: question regarding cacheline size

[Matthew Wilcox <matthew@wil.cx>]

On Thu, Sep 07, 2006 at 10:31:02AM +0200, Tejun Heo wrote:
> As the BIOS doesn't run after hotplugging cardbus card, the cache line 
> isn't configured and the controller ends up having 0 cache line size and 
> always using Read command.  When that happens, write performance drops 
> hard - the throughput is < 2Mbytes/s.
> 
> http://thread.gmane.org/gmane.linux.ide/12908/focus=12908
> 
> So, sata_sil24 driver has to program CLS if it's not already set, but 
> I'm not sure which number to punch in.  FWIW, sil3124 doesn't seem to 
> put restrictions on the values which can be used for CLS.  There are 
> several candidates...
> 
> * L1_CACHE_BYTES / 4 : this is used by init routine in yenta_socket.c. 
> It seems to be a sane default but I'm not sure whether L1 cache line 
> size always coincides with the size as seen from PCI bus.
> 
> * pci_cache_line_size in drivers/pci/pci.c : this is used for 
> pci_generic_prep_mwi() and can be overridden by arch specific code. 
> this seems more appropriate but is not exported.
> 
> For all involved commands - memory read line, memory read multiple and 
> memory write and invalidate - a value larger than actual cacheline size 
> doesn't hurt but a smaller value may.

Just call pci_set_mwi(), that'll make sure the cache line size is set
correctly.