From: Tejun Heo <htejun@gmail.com>
To: Matthew Wilcox <matthew@wil.cx>
Cc: linux-pci@atrey.karlin.mff.cuni.cz, Greg KH <greg@kroah.com>,
lkml <linux-kernel@vger.kernel.org>
Subject: Re: question regarding cacheline size
Date: Thu, 07 Sep 2006 13:20:22 +0200 [thread overview]
Message-ID: <45000076.4070005@gmail.com> (raw)
In-Reply-To: <20060907111120.GL2558@parisc-linux.org>
Matthew Wilcox wrote:
> Just call pci_set_mwi(), that'll make sure the cache line size is set
> correctly.
Sounds simple enough. Just two small worries though.
* It has an apparent side effect of setting PCI_COMMAND_INVALIDATE,
which should be okay in sil3124's case.
* The controller might have some restrictions on configurable cache line
size. This is the same for MWI, so I guess this problem is just imaginary.
For the time being, I'll go with pci_set_mwi() but IMHO it would be
better to have a pci helper for this purpose -
pci_config_cacheline_size() or something.
Thanks.
--
tejun
next prev parent reply other threads:[~2006-09-07 11:20 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2006-09-07 8:31 question regarding cacheline size Tejun Heo
2006-09-07 11:11 ` Matthew Wilcox
2006-09-07 11:20 ` Tejun Heo [this message]
2006-09-07 12:07 ` Russell King
2006-09-07 12:23 ` Matthew Wilcox
2006-09-07 12:33 ` Arjan van de Ven
2006-09-07 12:40 ` Matthew Wilcox
2006-09-07 12:53 ` Tejun Heo
2006-09-07 13:04 ` Matthew Wilcox
2006-09-07 13:19 ` Tejun Heo
2006-09-07 15:21 ` Grant Grundler
2006-09-07 15:47 ` Tejun Heo
2006-09-07 16:00 ` Jeff Garzik
2006-09-07 17:00 ` Matthew Wilcox
2006-09-07 16:04 ` Jeff Garzik
2006-09-22 23:47 ` Grant Grundler
2006-09-07 13:30 ` Jeff Garzik
2006-09-07 13:10 ` Russell King
2006-09-07 13:01 ` Arjan van de Ven
2006-09-07 13:02 ` Russell King
2006-09-07 11:59 ` linux-os (Dick Johnson)
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