From: Jeff Garzik <jgarzik@pobox.com>
To: Tejun Heo <htejun@gmail.com>
Cc: Grant Grundler <grundler@parisc-linux.org>,
Matthew Wilcox <matthew@wil.cx>,
Arjan van de Ven <arjan@infradead.org>,
linux-pci@atrey.karlin.mff.cuni.cz, Greg KH <greg@kroah.com>,
lkml <linux-kernel@vger.kernel.org>
Subject: Re: question regarding cacheline size
Date: Thu, 07 Sep 2006 12:00:39 -0400 [thread overview]
Message-ID: <45004227.8090200@pobox.com> (raw)
In-Reply-To: <45003F1B.7000302@gmail.com>
Tejun Heo wrote:
> arch/i386/pci/common.c overrides cacheline size to min 32 regardless of
> actual size. So, we seem to be using larger cacheline size for MWI
> already.
It clamps the minimum size to 32, yes, but on modern machines common.c
configures it to a larger size.
> Jeff pointed out that there actually are devices which limit CLS config.
> IMHO, making PCI configure CLS automatically and provide helpers to LLD
> to override it if necessary should cut it.
We still have to add a raft of quirks, if we start automatically
configurating CLS... Also, many PCI devices hardcode it to zero.
If we start configuring CLS automatically, I forsee a period of breakage...
Jeff
next prev parent reply other threads:[~2006-09-07 16:01 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2006-09-07 8:31 question regarding cacheline size Tejun Heo
2006-09-07 11:11 ` Matthew Wilcox
2006-09-07 11:20 ` Tejun Heo
2006-09-07 12:07 ` Russell King
2006-09-07 12:23 ` Matthew Wilcox
2006-09-07 12:33 ` Arjan van de Ven
2006-09-07 12:40 ` Matthew Wilcox
2006-09-07 12:53 ` Tejun Heo
2006-09-07 13:04 ` Matthew Wilcox
2006-09-07 13:19 ` Tejun Heo
2006-09-07 15:21 ` Grant Grundler
2006-09-07 15:47 ` Tejun Heo
2006-09-07 16:00 ` Jeff Garzik [this message]
2006-09-07 17:00 ` Matthew Wilcox
2006-09-07 16:04 ` Jeff Garzik
2006-09-22 23:47 ` Grant Grundler
2006-09-07 13:30 ` Jeff Garzik
2006-09-07 13:10 ` Russell King
2006-09-07 13:01 ` Arjan van de Ven
2006-09-07 13:02 ` Russell King
2006-09-07 11:59 ` linux-os (Dick Johnson)
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