[Intel IOMMU 03/10] clflush_cache_range now takes size param

["Keshavamurthy, Anil S" <anil.s.keshavamurthy@intel.com>]

[-- Attachment #1: clflush_cache_range.patch --]
[-- Type: text/plain, Size: 1727 bytes --]

	Introduce the size param for clflush_cache_range().

Signed-off-by: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>

---
 arch/x86_64/mm/pageattr.c       |    6 +++---
 include/asm-x86_64/cacheflush.h |    1 +
 2 files changed, 4 insertions(+), 3 deletions(-)

Index: linux-2.6.22-rc4-mm2/arch/x86_64/mm/pageattr.c
===================================================================
--- linux-2.6.22-rc4-mm2.orig/arch/x86_64/mm/pageattr.c	2007-06-18 15:45:39.000000000 -0700
+++ linux-2.6.22-rc4-mm2/arch/x86_64/mm/pageattr.c	2007-06-18 15:45:46.000000000 -0700
@@ -61,10 +61,10 @@
 	return base;
 } 
 
-static void cache_flush_page(void *adr)
+void clflush_cache_range(void *adr, int size)
 {
 	int i;
-	for (i = 0; i < PAGE_SIZE; i += boot_cpu_data.x86_clflush_size)
+	for (i = 0; i < size; i += boot_cpu_data.x86_clflush_size)
 		asm volatile("clflush (%0)" :: "r" (adr + i));
 }
 
@@ -80,7 +80,7 @@
 	list_for_each_entry(pg, l, lru) {
 		void *adr = page_address(pg);
 		if (cpu_has_clflush)
-			cache_flush_page(adr);
+			clflush_cache_range(adr, PAGE_SIZE);
 	}
 	__flush_tlb_all();
 }
Index: linux-2.6.22-rc4-mm2/include/asm-x86_64/cacheflush.h
===================================================================
--- linux-2.6.22-rc4-mm2.orig/include/asm-x86_64/cacheflush.h	2007-06-18 15:45:39.000000000 -0700
+++ linux-2.6.22-rc4-mm2/include/asm-x86_64/cacheflush.h	2007-06-18 15:45:46.000000000 -0700
@@ -27,6 +27,7 @@
 void global_flush_tlb(void); 
 int change_page_attr(struct page *page, int numpages, pgprot_t prot);
 int change_page_attr_addr(unsigned long addr, int numpages, pgprot_t prot);
+void clflush_cache_range(void *addr, int size);
 
 #ifdef CONFIG_DEBUG_RODATA
 void mark_rodata_ro(void);

--