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From: Andrew Morton <akpm@linux-foundation.org>
To: "Keshavamurthy, Anil S" <anil.s.keshavamurthy@intel.com>
Cc: linux-kernel@vger.kernel.org, ak@suse.de, gregkh@suse.de,
	muli@il.ibm.com, suresh.b.siddha@intel.com,
	arjan@linux.intel.com, ashok.raj@intel.com, davem@davemloft.net,
	clameter@sgi.com
Subject: Re: [Intel IOMMU 05/10] Intel IOMMU driver
Date: Mon, 25 Jun 2007 23:25:11 -0700	[thread overview]
Message-ID: <20070625232511.3fc07f8f.akpm@linux-foundation.org> (raw)
In-Reply-To: <20070619213808.716432000@askeshav-devel.jf.intel.com>

On Tue, 19 Jun 2007 14:37:06 -0700 "Keshavamurthy, Anil S" <anil.s.keshavamurthy@intel.com> wrote:

> +/*
> + * Decoding Capability Register
> + */
> +#define cap_read_drain(c)	(((c) >> 55) & 1)
> +#define cap_write_drain(c)	(((c) >> 54) & 1)
> +#define cap_max_amask_val(c)	(((c) >> 48) & 0x3f)
> +#define cap_num_fault_regs(c)	((((c) >> 40) & 0xff) + 1)
> +#define cap_pgsel_inv(c)	(((c) >> 39) & 1)
> +
> +#define cap_super_page_val(c)	(((c) >> 34) & 0xf)
> +#define cap_super_offset(c)	(((find_first_bit(&cap_super_page_val(c), 4)) \
> +					* OFFSET_STRIDE) + 21)
> +
> +#define cap_fault_reg_offset(c)	((((c) >> 24) & 0x3ff) * 16)
> +#define cap_max_fault_reg_offset(c) \
> +	(cap_fault_reg_offset(c) + cap_num_fault_regs(c) * 16)
> +
> +#define cap_zlr(c)		(((c) >> 22) & 1)
> +#define cap_isoch(c)		(((c) >> 23) & 1)
> +#define cap_mgaw(c)		((((c) >> 16) & 0x3f) + 1)
> +#define cap_sagaw(c)		(((c) >> 8) & 0x1f)
> +#define cap_caching_mode(c)	(((c) >> 7) & 1)
> +#define cap_phmr(c)		(((c) >> 6) & 1)
> +#define cap_plmr(c)		(((c) >> 5) & 1)
> +#define cap_rwbf(c)		(((c) >> 4) & 1)
> +#define cap_afl(c)		(((c) >> 3) & 1)
> +#define cap_ndoms(c)		(((unsigned long)1) << (4 + 2 * ((c) & 0x7)))
> +/*
> + * Extended Capability Register
> + */
> +
> +#define ecap_niotlb_iunits(e)	((((e) >> 24) & 0xff) + 1)
> +#define ecap_iotlb_offset(e) 	((((e) >> 8) & 0x3ff) * 16)
> +#define ecap_max_iotlb_offset(e) \
> +	(ecap_iotlb_offset(e) + ecap_niotlb_iunits(e) * 16)
> +#define ecap_coherent(e)	((e) & 0x1)

None of these actually _need_ to be macros and it would be better to 
implement them in C.  That way things are more self-documenting, more
pleasant to read, more likely to get commented and you'll fix the
two bugs wherein the argument to a macro is evaluated more than once.


  parent reply	other threads:[~2007-06-26  6:25 UTC|newest]

Thread overview: 65+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2007-06-19 21:37 [Intel IOMMU 00/10] Intel IOMMU support, take #2 Keshavamurthy, Anil S
2007-06-19 21:37 ` [Intel IOMMU 01/10] DMAR detection and parsing logic Keshavamurthy, Anil S
2007-07-04  9:18   ` Peter Zijlstra
2007-07-04 10:04     ` Andrew Morton
2007-07-04 10:14       ` Peter Zijlstra
2007-06-19 21:37 ` [Intel IOMMU 02/10] PCI generic helper function Keshavamurthy, Anil S
2007-06-26  5:49   ` Andrew Morton
2007-06-26 14:44     ` Keshavamurthy, Anil S
2007-06-19 21:37 ` [Intel IOMMU 03/10] clflush_cache_range now takes size param Keshavamurthy, Anil S
2007-06-19 21:37 ` [Intel IOMMU 04/10] IOVA allocation and management routines Keshavamurthy, Anil S
2007-06-26  6:07   ` Andrew Morton
2007-06-26 16:16     ` Keshavamurthy, Anil S
2007-06-19 21:37 ` [Intel IOMMU 05/10] Intel IOMMU driver Keshavamurthy, Anil S
2007-06-19 23:32   ` Christoph Lameter
2007-06-19 23:50     ` Keshavamurthy, Anil S
2007-06-19 23:56       ` Christoph Lameter
2007-06-26  6:32     ` Andrew Morton
2007-06-26 16:29       ` Keshavamurthy, Anil S
2007-06-26  6:25   ` Andrew Morton [this message]
2007-06-26 16:33     ` Keshavamurthy, Anil S
2007-06-26  6:30   ` Andrew Morton
2007-06-19 21:37 ` [Intel IOMMU 06/10] Avoid memory allocation failures in dma map api calls Keshavamurthy, Anil S
2007-06-19 23:25   ` Christoph Lameter
2007-06-19 23:27     ` Arjan van de Ven
2007-06-19 23:34       ` Christoph Lameter
2007-06-20  0:02         ` Arjan van de Ven
2007-06-20  8:06   ` Peter Zijlstra
2007-06-20 13:03     ` Arjan van de Ven
2007-06-20 17:30       ` Siddha, Suresh B
2007-06-20 18:05         ` Peter Zijlstra
2007-06-20 19:14           ` Arjan van de Ven
2007-06-20 20:08             ` Peter Zijlstra
2007-06-20 23:03               ` Keshavamurthy, Anil S
2007-06-21  6:10                 ` Peter Zijlstra
2007-06-21  6:11                   ` Arjan van de Ven
2007-06-21  6:29                     ` Peter Zijlstra
2007-06-21  6:37                       ` Keshavamurthy, Anil S
2007-06-21  7:13                         ` Peter Zijlstra
2007-06-21 19:51                           ` Keshavamurthy, Anil S
2007-06-21  6:30                     ` Keshavamurthy, Anil S
2007-06-26  5:34     ` Andrew Morton
2007-06-19 21:37 ` [Intel IOMMU 07/10] Intel iommu cmdline option - forcedac Keshavamurthy, Anil S
2007-06-19 21:37 ` [Intel IOMMU 08/10] DMAR fault handling support Keshavamurthy, Anil S
2007-06-19 21:37 ` [Intel IOMMU 09/10] Iommu Gfx workaround Keshavamurthy, Anil S
2007-06-19 21:37 ` [Intel IOMMU 10/10] Iommu floppy workaround Keshavamurthy, Anil S
2007-06-26  6:42   ` Andrew Morton
2007-06-26 10:37     ` Andi Kleen
2007-06-26 19:25       ` Keshavamurthy, Anil S
2007-06-26 16:26     ` Keshavamurthy, Anil S
2007-06-26  6:45 ` [Intel IOMMU 00/10] Intel IOMMU support, take #2 Andrew Morton
2007-06-26  7:12   ` Andi Kleen
2007-06-26 11:13     ` Muli Ben-Yehuda
2007-06-26 15:03       ` Arjan van de Ven
2007-06-26 15:11         ` Muli Ben-Yehuda
2007-06-26 15:48           ` Keshavamurthy, Anil S
2007-06-26 16:00             ` Muli Ben-Yehuda
2007-06-26 15:56       ` Andi Kleen
2007-06-26 15:09         ` Muli Ben-Yehuda
2007-06-26 15:36           ` Andi Kleen
2007-06-26 15:15         ` Arjan van de Ven
2007-06-26 15:33           ` Andi Kleen
2007-06-26 16:25             ` Arjan van de Ven
2007-06-26 17:31               ` Andi Kleen
2007-06-26 20:10                 ` Jesse Barnes
2007-06-26 22:35                   ` Andi Kleen

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