Re: [patch 2.6.22-git5 0/4] MMC-over-SPI

[David Brownell <david-b-yBeKhBN/0LDR7s880joybQ@public.gmane.org>]

On Wednesday 18 July 2007, Pierre Ossman wrote:
> On Tue, 17 Jul 2007 09:11:15 -0700
> David Brownell <david-b-yBeKhBN/0LDR7s880joybQ@public.gmane.org> wrote:
> 
> > Ideally, someone with access to full MMC and SD specs can see
> > what they say about the SPI clocking.  The simplified SD specs
> > omit the timing diagrams.
> >  
> 
> I can probably help out there.
> 
> According to the specs, both mode 0 and mode 3 are valid. The idle
> polarity simply isn't specified, only that data shall be sampled on
> rising edge. Hence mode 0 or 3.

Thanks.  In that case, I'm thinking there *IS* a bug of some kind
in the controller driver Anton is using, else mode 3 would work
for him like it (evidently) works for everyone else.

I'll see about making time to see if mode 0 works for me too; but
even if it does, I'd prefer to leave the driver the way it is now
instead of changing it to cover up for that mpc83xx bug ... plus,
I just like CPHA=1 modes better because they don't need to start
with that strange half-clock.  ;)

- Dave

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