[PATCH] 1/3: MCA/MCE correctable error handling

[PATCH] 1/3: MCA/MCE correctable error handling

[Christoph Egger]

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This is patch 1/3.

Signed-off-by: Christoph Egger <Christoph.Egger@amd.com>



-- 
AMD Saxony, Dresden, Germany
Operating System Research Center

Legal Information:
AMD Saxony Limited Liability Company & Co. KG
Sitz (Geschäftsanschrift):
   Wilschdorfer Landstr. 101, 01109 Dresden, Deutschland
Registergericht Dresden: HRA 4896
vertretungsberechtigter Komplementär:
   AMD Saxony LLC (Sitz Wilmington, Delaware, USA)
Geschäftsführer der AMD Saxony LLC:
   Dr. Hans-R. Deppe, Thomas McCoy

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diff -r 256160ff19b7 xen/arch/x86/cpu/mcheck/mce.c
--- a/xen/arch/x86/cpu/mcheck/mce.c	Thu Aug 16 13:27:59 2007 +0100
+++ b/xen/arch/x86/cpu/mcheck/mce.c	Thu Aug 16 16:34:45 2007 +0000
@@ -15,7 +15,7 @@
 #include "mce.h"
 
 int mce_disabled = 0;
-int nr_mce_banks;
+unsigned int nr_mce_banks;
 
 /* Handle unconfigured int18 (should never happen) */
 static fastcall void unexpected_machine_check(struct cpu_user_regs * regs, long error_code)
@@ -29,35 +29,49 @@ void fastcall (*machine_check_vector)(st
 /* This has to be run for each processor */
 void mcheck_init(struct cpuinfo_x86 *c)
 {
-	if (mce_disabled==1)
+	uint32_t mca, mce;
+
+	if (mce_disabled == 1) {
+		printk("MCE support disabled by bootparam\n");
 		return;
+	}
+
+	/* Xen requires an i686 class CPU. So this
+	 * check should be almost always true here. */
+	mca = cpu_has(c, X86_FEATURE_MCA);
+	mce = cpu_has(c, X86_FEATURE_MCE);
+
+	if (!mca && !mce) {
+		printk(KERN_INFO "CPU%i: No machine check support available\n",
+			smp_processor_id());
+		return;
+	}
 
 	switch (c->x86_vendor) {
-		case X86_VENDOR_AMD:
-			if (c->x86==6 || c->x86==15)
-				amd_mcheck_init(c);
-			break;
+	case X86_VENDOR_AMD:
+		amd_mcheck_init(c);
+		break;
 
-		case X86_VENDOR_INTEL:
+	case X86_VENDOR_INTEL:
 #ifndef CONFIG_X86_64
-			if (c->x86==5)
-				intel_p5_mcheck_init(c);
-			if (c->x86==6)
-				intel_p6_mcheck_init(c);
+		if (c->x86==5)
+			intel_p5_mcheck_init(c);
+		if (c->x86==6)
+			intel_p6_mcheck_init(c);
 #endif
-			if (c->x86==15)
-				intel_p4_mcheck_init(c);
-			break;
+		if (c->x86==15)
+			intel_p4_mcheck_init(c);
+		break;
 
 #ifndef CONFIG_X86_64
-		case X86_VENDOR_CENTAUR:
-			if (c->x86==5)
-				winchip_mcheck_init(c);
-			break;
+	case X86_VENDOR_CENTAUR:
+		if (c->x86==5)
+			winchip_mcheck_init(c);
+		break;
 #endif
 
-		default:
-			break;
+	default:
+		break;
 	}
 }
 
diff -r 256160ff19b7 xen/arch/x86/cpu/mcheck/mce.h
--- a/xen/arch/x86/cpu/mcheck/mce.h	Thu Aug 16 13:27:59 2007 +0100
+++ b/xen/arch/x86/cpu/mcheck/mce.h	Thu Aug 16 16:34:45 2007 +0000
@@ -10,5 +10,4 @@ extern fastcall void (*machine_check_vec
 extern fastcall void (*machine_check_vector)(struct cpu_user_regs *, long error_code);
 
 extern int mce_disabled __initdata;
-extern int nr_mce_banks;
-
+extern unsigned int nr_mce_banks;

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