[U-Boot-Users] [PATCH9] microblaze EMAC support

[U-Boot-Users] [PATCH9] microblaze EMAC support

[Michal Simek]

DESC: Xilinx Emac support

Signed-off-by: Michal Simek <monstr@monstr.eu>

Note: driver is tested for Microblaze CPU. Please test it for PowerPC405 and then remove code 

diff --git a/drivers/net/xilinx_emac.c b/drivers/net/xilinx_emac.c
new file mode 100644
index 0000000..36e627a
--- /dev/null
+++ b/drivers/net/xilinx_emac.c
@@ -0,0 +1,374 @@
+/*
+ * (C) Copyright 2007 Michal Simek
+ *
+ * Michal SIMEK <monstr@monstr.eu>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Based on Xilinx drivers
+ *
+ */
+
+#include <config.h>
+#include <common.h>
+#include <net.h>
+#include <asm/io.h>
+#include "xilinx_emac.h"
+
+#ifdef XILINX_EMAC
+
+#undef DEBUG
+
+#define ENET_MAX_MTU           PKTSIZE
+#define ENET_ADDR_LENGTH       6
+
+static unsigned int etherrxbuff[PKTSIZE_ALIGN/4]; /* Receive buffer */
+
+static u8 emacaddr[ENET_ADDR_LENGTH] = { 0x00, 0x0a, 0x35, 0x00, 0x22, 0x01 };
+
+static xemac emac;
+
+void eth_halt(void)
+{
+#ifdef DEBUG
+       puts ("eth_halt\n");
+#endif
+}
+
+int eth_init(bd_t * bis)
+{
+       u32 helpreg;
+#ifdef DEBUG
+       printf("EMAC Initialization Started\n\r");
+#endif
+       if (emac.isstarted) {
+               puts("Emac is started\n");
+               return 0;
+       }
+
+       memset (&emac, 0, sizeof (xemac));
+
+       emac.baseaddress = XILINX_EMAC_BASEADDR;
+
+       /* Setting up FIFOs */
+       emac.recvfifo.regbaseaddress = emac.baseaddress +
+                                       XEM_PFIFO_RXREG_OFFSET;
+       emac.recvfifo.databaseaddress = emac.baseaddress +
+                                       XEM_PFIFO_RXDATA_OFFSET;
+       out_be32 (emac.recvfifo.regbaseaddress, XPF_RESET_FIFO_MASK);
+
+       emac.sendfifo.regbaseaddress = emac.baseaddress +
+                                       XEM_PFIFO_TXREG_OFFSET;
+       emac.sendfifo.databaseaddress = emac.baseaddress +
+                                       XEM_PFIFO_TXDATA_OFFSET;
+       out_be32 (emac.sendfifo.regbaseaddress, XPF_RESET_FIFO_MASK);
+
+       /* Reset the entire IPIF */
+       out_be32 (emac.baseaddress + XIIF_V123B_RESETR_OFFSET,
+                                       XIIF_V123B_RESET_MASK);
+
+       /* Stopping EMAC for setting up MAC */
+       helpreg = in_be32 (emac.baseaddress + XEM_ECR_OFFSET);
+       helpreg &= ~(XEM_ECR_XMIT_ENABLE_MASK | XEM_ECR_RECV_ENABLE_MASK);
+       out_be32 (emac.baseaddress + XEM_ECR_OFFSET, helpreg);
+
+       if (!getenv("ethaddr")) {
+               memcpy(bis->bi_enetaddr, emacaddr, ENET_ADDR_LENGTH);
+       }
+
+       /* Set the device station address high and low registers */
+       helpreg = (bis->bi_enetaddr[0] << 8) | bis->bi_enetaddr[1];
+       out_be32 (emac.baseaddress + XEM_SAH_OFFSET, helpreg);
+       helpreg = (bis->bi_enetaddr[2] << 24) | (bis->bi_enetaddr[3] << 16) |
+                       (bis->bi_enetaddr[4] << 8) | bis->bi_enetaddr[5];
+       out_be32 (emac.baseaddress + XEM_SAL_OFFSET, helpreg);
+
+
+       helpreg = XEM_ECR_UNICAST_ENABLE_MASK | XEM_ECR_BROAD_ENABLE_MASK |
+               XEM_ECR_FULL_DUPLEX_MASK | XEM_ECR_XMIT_FCS_ENABLE_MASK |
+               XEM_ECR_XMIT_PAD_ENABLE_MASK | XEM_ECR_PHY_ENABLE_MASK;
+       out_be32 (emac.baseaddress + XEM_ECR_OFFSET, helpreg);
+
+       emac.isstarted = 1;
+
+       /* Enable the transmitter, and receiver */
+       helpreg = in_be32 (emac.baseaddress + XEM_ECR_OFFSET);
+       helpreg &= ~(XEM_ECR_XMIT_RESET_MASK | XEM_ECR_RECV_RESET_MASK);
+       helpreg |= (XEM_ECR_XMIT_ENABLE_MASK | XEM_ECR_RECV_ENABLE_MASK);
+       out_be32 (emac.baseaddress + XEM_ECR_OFFSET, helpreg);
+
+       printf("EMAC Initialization complete\n\r");
+       return 0;
+}
+
+int eth_send(volatile void *ptr, int len)
+{
+       u32 intrstatus;
+       u32 xmitstatus;
+       u32 fifocount;
+       u32 wordcount;
+       u32 extrabytecount;
+       u32 *wordbuffer = (u32 *) ptr;
+
+       if (len > ENET_MAX_MTU)
+               len = ENET_MAX_MTU;
+
+       /*
+        * Check for overruns and underruns for the transmit status and length
+        * FIFOs and make sure the send packet FIFO is not deadlocked.
+        * Any of these conditions is bad enough that we do not want to
+        * continue. The upper layer software should reset the device to resolve+        * the error.
+        */
+       intrstatus = in_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET);
+       if (intrstatus & (XEM_EIR_XMIT_SFIFO_OVER_MASK |
+                       XEM_EIR_XMIT_LFIFO_OVER_MASK)) {
+#ifdef DEBUG
+               puts ("Transmitting overrun error\n");
+#endif
+               return 0;
+       } else if (intrstatus & (XEM_EIR_XMIT_SFIFO_UNDER_MASK |
+                       XEM_EIR_XMIT_LFIFO_UNDER_MASK)) {
+#ifdef DEBUG
+               puts ("Transmitting underrun error\n");
+#endif
+               return 0;
+       } else if (in_be32 (emac.sendfifo.regbaseaddress +
+                       XPF_COUNT_STATUS_REG_OFFSET) & XPF_DEADLOCK_MASK) {
+#ifdef DEBUG
+               puts("Transmitting fifo error\n");
+#endif
+               return 0;
+       }
+
+       /*
+        * Before writing to the data FIFO, make sure the length FIFO is not
+        * full. The data FIFO might not be full yet even though the length FIFO+        * is. This avoids an overrun condition on the length FIFO and keeps the+        * FIFOs in sync.
+        *
+        * Clear the latched LFIFO_FULL bit so next time around the most
+        * current status is represented
+        */
+       if (intrstatus & XEM_EIR_XMIT_LFIFO_FULL_MASK) {
+               out_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET,
+                       intrstatus & XEM_EIR_XMIT_LFIFO_FULL_MASK);
+#ifdef DEBUG
+               puts ("Fifo is full\n");
+#endif
+               return 0;
+       }
+
+       /* get the count of how many words may be inserted into the FIFO */
+       fifocount = in_be32 (emac.sendfifo.regbaseaddress +
+                               XPF_COUNT_STATUS_REG_OFFSET) & XPF_COUNT_MASK;
+       wordcount = len >> 2;
+       extrabytecount = len & 0x3;
+
+       if (fifocount < wordcount) {
+#ifdef DEBUG
+               puts ("Sending packet is larger then size of FIFO\n");
+#endif
+               return 0;
+       }
+
+       for (fifocount = 0; fifocount < wordcount; fifocount++) {
+               out_be32 (emac.sendfifo.databaseaddress, wordbuffer[fifocount]);+       }
+       if (extrabytecount > 0) {
+               u32 lastword = 0;
+               u8 *extrabytesbuffer = (u8 *) (wordbuffer + wordcount);
+
+               if (extrabytecount == 1) {
+                       lastword = extrabytesbuffer[0] << 24;
+               } else if (extrabytecount == 2) {
+                       lastword = extrabytesbuffer[0] << 24 |
+                               extrabytesbuffer[1] << 16;
+               } else if (extrabytecount == 3) {
+                       lastword = extrabytesbuffer[0] << 24 |
+                               extrabytesbuffer[1] << 16 |
+                               extrabytesbuffer[2] << 8;
+               }
+               out_be32 (emac.sendfifo.databaseaddress, lastword);
+       }
+
+       /* Loop on the MAC's status to wait for any pause to complete */
+       intrstatus = in_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET);
+       while ((intrstatus & XEM_EIR_XMIT_PAUSE_MASK) != 0) {
+               intrstatus = in_be32 ((emac.baseaddress) +
+                                       XIIF_V123B_IISR_OFFSET);
+               /* Clear the pause status from the transmit status register */
+               out_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET,
+                               intrstatus & XEM_EIR_XMIT_PAUSE_MASK);
+       }
+
+       /*
+        * Set the MAC's transmit packet length register to tell it to transmit
+        */
+       out_be32 (emac.baseaddress + XEM_TPLR_OFFSET, len);
+
+       /*
+        * Loop on the MAC's status to wait for the transmit to complete.
+        * The transmit status is in the FIFO when the XMIT_DONE bit is set.
+        */
+       do {
+               intrstatus = in_be32 ((emac.baseaddress) +
+                                               XIIF_V123B_IISR_OFFSET);
+       }
+       while ((intrstatus & XEM_EIR_XMIT_DONE_MASK) == 0);
+
+       xmitstatus = in_be32 (emac.baseaddress + XEM_TSR_OFFSET);
+
+       if (intrstatus & (XEM_EIR_XMIT_SFIFO_OVER_MASK |
+                                       XEM_EIR_XMIT_LFIFO_OVER_MASK)) {
+#ifdef DEBUG
+               puts ("Transmitting overrun error\n");
+#endif
+               return 0;
+       } else if (intrstatus & (XEM_EIR_XMIT_SFIFO_UNDER_MASK |
+                                       XEM_EIR_XMIT_LFIFO_UNDER_MASK)) {
+#ifdef DEBUG
+               puts ("Transmitting underrun error\n");
+#endif
+               return 0;
+       }
+
+       /* Clear the interrupt status register of transmit statuses */
+       out_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET,
+                               intrstatus & XEM_EIR_XMIT_ALL_MASK);
+
+       /*
+        * Collision errors are stored in the transmit status register
+        * instead of the interrupt status register
+        */
+       if ((xmitstatus & XEM_TSR_EXCESS_DEFERRAL_MASK) ||
+                               (xmitstatus & XEM_TSR_LATE_COLLISION_MASK)) {
+#ifdef DEBUG
+               puts ("Transmitting collision error\n");
+#endif
+               return 0;
+       }
+       return 1;
+}
+
+int eth_rx(void)
+{
+       u32 pktlength;
+       u32 intrstatus;
+       u32 fifocount;
+       u32 wordcount;
+       u32 extrabytecount;
+       u32 lastword;
+       u8 *extrabytesbuffer;
+
+       if (in_be32 (emac.recvfifo.regbaseaddress + XPF_COUNT_STATUS_REG_OFFSET)+                       & XPF_DEADLOCK_MASK) {
+               out_be32 (emac.recvfifo.regbaseaddress, XPF_RESET_FIFO_MASK);
+#ifdef DEBUG
+               puts ("Receiving FIFO deadlock\n");
+#endif
+               return 0;
+       }
+
+       /*
+        * Get the interrupt status to know what happened (whether an error
+        * occurred and/or whether frames have been received successfully).
+        * When clearing the intr status register, clear only statuses that
+        * pertain to receive.
+        */
+       intrstatus = in_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET);
+       /*
+        * Before reading from the length FIFO, make sure the length FIFO is not+        * empty. We could cause an underrun error if we try to read from an
+        * empty FIFO.
+        */
+       if (!(intrstatus & XEM_EIR_RECV_DONE_MASK)) {
+#ifdef DEBUG
+               /* puts("Receiving FIFO is empty\n"); */
+#endif
+               return 0;
+       }
+
+       /*
+        * Determine, from the MAC, the length of the next packet available
+        * in the data FIFO (there should be a non-zero length here)
+        */
+       pktlength = in_be32 (emac.baseaddress + XEM_RPLR_OFFSET);
+       if (!pktlength) {
+               return 0;
+       }
+
+       /*
+        * Write the RECV_DONE bit in the status register to clear it. This bit
+        * indicates the RPLR is non-empty, and we know it's set@this point.
+        * We clear it so that subsequent entry into this routine will reflect
+        * the current status. This is done because the non-empty bit is latched+        * in the IPIF, which means it may indicate a non-empty condition even
+        * though there is something in the FIFO.
+        */
+       out_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET,
+                                               XEM_EIR_RECV_DONE_MASK);
+
+       fifocount = in_be32 (emac.recvfifo.regbaseaddress +
+                               XPF_COUNT_STATUS_REG_OFFSET) & XPF_COUNT_MASK;
+
+       if ((fifocount * 4) < pktlength) {
+#ifdef DEBUG
+               puts ("Receiving FIFO is smaller than packet size.\n");
+#endif
+               return 0;
+       }
+
+       wordcount = pktlength >> 2;
+       extrabytecount = pktlength & 0x3;
+
+       for (fifocount = 0; fifocount < wordcount; fifocount++) {
+               etherrxbuff[fifocount] =
+                               in_be32 (emac.recvfifo.databaseaddress);
+       }
+
+       /*
+        * if there are extra bytes to handle, read the last word from the FIFO
+        * and insert the extra bytes into the buffer
+        */
+       if (extrabytecount > 0) {
+               extrabytesbuffer = (u8 *) (etherrxbuff + wordcount);
+
+               lastword = in_be32 (emac.recvfifo.databaseaddress);
+
+               /*
+                * one extra byte in the last word, put the byte into the next
+                * location of the buffer, bytes in a word of the FIFO are
+                * ordered from most significant byte to least
+                */
+               if (extrabytecount == 1) {
+                       extrabytesbuffer[0] = (u8) (lastword >> 24);
+               } else if (extrabytecount == 2) {
+                       extrabytesbuffer[0] = (u8) (lastword >> 24);
+                       extrabytesbuffer[1] = (u8) (lastword >> 16);
+               } else if (extrabytecount == 3) {
+                       extrabytesbuffer[0] = (u8) (lastword >> 24);
+                       extrabytesbuffer[1] = (u8) (lastword >> 16);
+                       extrabytesbuffer[2] = (u8) (lastword >> 8);
+               }
+       }
+       NetReceive((uchar *)etherrxbuff, pktlength);
+       return 1;
+}
+#endif
diff --git a/drivers/net/xilinx_emac.h b/drivers/net/xilinx_emac.h
new file mode 100644
index 0000000..966598e
--- /dev/null
+++ b/drivers/net/xilinx_emac.h
@@ -0,0 +1,148 @@
+/*
+ * (C) Copyright 2007 Michal Simek
+ *
+ * Michal SIMEK <monstr@monstr.eu>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Based on Xilinx drivers
+ *
+ */
+
+typedef struct {
+       u32 regbaseaddress;     /* Base address of registers */
+       u32 databaseaddress;    /* Base address of data for FIFOs */
+} xpacketfifov100b;
+
+typedef struct {
+       u32 baseaddress;        /* Base address (of IPIF) */
+       u32 isstarted;          /* Device is currently started 0-no, 1-yes */
+       xpacketfifov100b recvfifo;      /* FIFO used to receive frames */
+       xpacketfifov100b sendfifo;      /* FIFO used to send frames */
+} xemac;
+
+#define XIIF_V123B_IISR_OFFSET 32UL /* IP interrupt status register */
+#define XIIF_V123B_RESET_MASK          0xAUL
+#define XIIF_V123B_RESETR_OFFSET       64UL /* reset register */
+
+/* This constant is used with the Reset Register */
+#define XPF_RESET_FIFO_MASK            0x0000000A
+#define XPF_COUNT_STATUS_REG_OFFSET    4UL
+
+/* These constants are used with the Occupancy/Vacancy Count Register. This
+ * register also contains FIFO status */
+#define XPF_COUNT_MASK                 0x0000FFFF
+#define XPF_DEADLOCK_MASK              0x20000000
+
+/* Offset of the MAC registers from the IPIF base address */
+#define XEM_REG_OFFSET         0x1100UL
+
+/*
+ * Register offsets for the Ethernet MAC. Each register is 32 bits.
+ */
+#define XEM_ECR_OFFSET (XEM_REG_OFFSET + 0x4)  /* MAC Control */
+#define XEM_SAH_OFFSET (XEM_REG_OFFSET + 0xC)  /* Station addr, high */
+#define XEM_SAL_OFFSET (XEM_REG_OFFSET + 0x10) /* Station addr, low */
+#define XEM_RPLR_OFFSET        (XEM_REG_OFFSET + 0x1C) /* Rx packet length */
+#define XEM_TPLR_OFFSET        (XEM_REG_OFFSET + 0x20) /* Tx packet length */
+#define XEM_TSR_OFFSET (XEM_REG_OFFSET + 0x24) /* Tx status */
+
+
+
+#define XEM_PFIFO_OFFSET       0x2000UL
+/* Tx registers */
+#define XEM_PFIFO_TXREG_OFFSET (XEM_PFIFO_OFFSET + 0x0)
+/* Rx registers */
+#define XEM_PFIFO_RXREG_OFFSET (XEM_PFIFO_OFFSET + 0x10)
+/* Tx keyhole */
+#define XEM_PFIFO_TXDATA_OFFSET        (XEM_PFIFO_OFFSET + 0x100)
+/* Rx keyhole */
+#define XEM_PFIFO_RXDATA_OFFSET        (XEM_PFIFO_OFFSET + 0x200)
+
+
+/*
+ * EMAC Interrupt Registers (Status and Enable) masks. These registers are
+ * part of the IPIF IP Interrupt registers
+ */
+/* A mask for all transmit interrupts, used in polled mode */
+#define XEM_EIR_XMIT_ALL_MASK  (XEM_EIR_XMIT_DONE_MASK |\
+                                XEM_EIR_XMIT_ERROR_MASK | \
+                                XEM_EIR_XMIT_SFIFO_EMPTY_MASK |\
+                                XEM_EIR_XMIT_LFIFO_FULL_MASK)
+
+/* Xmit complete */
+#define XEM_EIR_XMIT_DONE_MASK         0x00000001UL
+/* Recv complete */
+#define XEM_EIR_RECV_DONE_MASK         0x00000002UL
+/* Xmit error */
+#define XEM_EIR_XMIT_ERROR_MASK                0x00000004UL
+/* Recv error */
+#define XEM_EIR_RECV_ERROR_MASK                0x00000008UL
+/* Xmit status fifo empty */
+#define XEM_EIR_XMIT_SFIFO_EMPTY_MASK  0x00000010UL
+/* Recv length fifo empty */
+#define XEM_EIR_RECV_LFIFO_EMPTY_MASK  0x00000020UL
+/* Xmit length fifo full */
+#define XEM_EIR_XMIT_LFIFO_FULL_MASK   0x00000040UL
+/* Recv length fifo overrun */
+#define XEM_EIR_RECV_LFIFO_OVER_MASK   0x00000080UL
+/* Recv length fifo underrun */
+#define XEM_EIR_RECV_LFIFO_UNDER_MASK  0x00000100UL
+/* Xmit status fifo overrun */
+#define XEM_EIR_XMIT_SFIFO_OVER_MASK   0x00000200UL
+/* Transmit status fifo underrun */
+#define XEM_EIR_XMIT_SFIFO_UNDER_MASK  0x00000400UL
+/* Transmit length fifo overrun */
+#define XEM_EIR_XMIT_LFIFO_OVER_MASK   0x00000800UL
+/* Transmit length fifo underrun */
+#define XEM_EIR_XMIT_LFIFO_UNDER_MASK  0x00001000UL
+/* Transmit pause pkt received */
+#define XEM_EIR_XMIT_PAUSE_MASK                0x00002000UL
+
+/*
+ * EMAC Control Register (ECR)
+ */
+/* Full duplex mode */
+#define XEM_ECR_FULL_DUPLEX_MASK        0x80000000UL
+/* Reset transmitter */
+#define XEM_ECR_XMIT_RESET_MASK                 0x40000000UL
+/* Enable transmitter */
+#define XEM_ECR_XMIT_ENABLE_MASK        0x20000000UL
+/* Reset receiver */
+#define XEM_ECR_RECV_RESET_MASK                 0x10000000UL
+/* Enable receiver */
+#define XEM_ECR_RECV_ENABLE_MASK        0x08000000UL
+/* Enable PHY */
+#define XEM_ECR_PHY_ENABLE_MASK                 0x04000000UL
+/* Enable xmit pad insert */
+#define XEM_ECR_XMIT_PAD_ENABLE_MASK    0x02000000UL
+/* Enable xmit FCS insert */
+#define XEM_ECR_XMIT_FCS_ENABLE_MASK    0x01000000UL
+/* Enable unicast addr */
+#define XEM_ECR_UNICAST_ENABLE_MASK     0x00020000UL
+/* Enable broadcast addr */
+#define XEM_ECR_BROAD_ENABLE_MASK       0x00008000UL
+
+/*
+ * Transmit Status Register (TSR)
+ */
+/* Transmit excess deferral */
+#define XEM_TSR_EXCESS_DEFERRAL_MASK   0x80000000UL
+/* Transmit late collision */
+#define XEM_TSR_LATE_COLLISION_MASK    0x01000000UL

[U-Boot-Users] [PATCH9] microblaze EMAC support

[Grant Likely]

On 8/30/07, Michal Simek <Monstr@seznam.cz> wrote:
> DESC: Xilinx Emac support
>
> Signed-off-by: Michal Simek <monstr@monstr.eu>

Another good looking driver.  All my comments are minor ones.

>
> Note: driver is tested for Microblaze CPU. Please test it for PowerPC405 and then remove code
>
> diff --git a/drivers/net/xilinx_emac.c b/drivers/net/xilinx_emac.c
> new file mode 100644
> index 0000000..36e627a
> --- /dev/null
> +++ b/drivers/net/xilinx_emac.c
> @@ -0,0 +1,374 @@
> +
> +#include <config.h>
> +#include <common.h>
> +#include <net.h>
> +#include <asm/io.h>
> +#include "xilinx_emac.h"
> +
> +#ifdef XILINX_EMAC

Need CONFIG_ prefix.

> +
> +#undef DEBUG
> +
> +#define ENET_MAX_MTU           PKTSIZE
> +#define ENET_ADDR_LENGTH       6
> +
> +static unsigned int etherrxbuff[PKTSIZE_ALIGN/4]; /* Receive buffer */
> +
> +static u8 emacaddr[ENET_ADDR_LENGTH] = { 0x00, 0x0a, 0x35, 0x00, 0x22, 0x01 };
> +
> +static xemac emac;
> +
> +void eth_halt(void)
> +{
> +#ifdef DEBUG
> +       puts ("eth_halt\n");
> +#endif

debug()

> +}
> +
> +int eth_init(bd_t * bis)
> +{
> +       u32 helpreg;
> +#ifdef DEBUG
> +       printf("EMAC Initialization Started\n\r");
> +#endif

debug()

> +       if (emac.isstarted) {
> +               puts("Emac is started\n");
> +               return 0;
> +       }
> +
> +       memset (&emac, 0, sizeof (xemac));
> +
> +       emac.baseaddress = XILINX_EMAC_BASEADDR;
> +
> +       /* Setting up FIFOs */
> +       emac.recvfifo.regbaseaddress = emac.baseaddress +
> +                                       XEM_PFIFO_RXREG_OFFSET;
> +       emac.recvfifo.databaseaddress = emac.baseaddress +
> +                                       XEM_PFIFO_RXDATA_OFFSET;
> +       out_be32 (emac.recvfifo.regbaseaddress, XPF_RESET_FIFO_MASK);
> +
> +       emac.sendfifo.regbaseaddress = emac.baseaddress +
> +                                       XEM_PFIFO_TXREG_OFFSET;
> +       emac.sendfifo.databaseaddress = emac.baseaddress +
> +                                       XEM_PFIFO_TXDATA_OFFSET;
> +       out_be32 (emac.sendfifo.regbaseaddress, XPF_RESET_FIFO_MASK);
> +
> +       /* Reset the entire IPIF */
> +       out_be32 (emac.baseaddress + XIIF_V123B_RESETR_OFFSET,
> +                                       XIIF_V123B_RESET_MASK);
> +
> +       /* Stopping EMAC for setting up MAC */
> +       helpreg = in_be32 (emac.baseaddress + XEM_ECR_OFFSET);
> +       helpreg &= ~(XEM_ECR_XMIT_ENABLE_MASK | XEM_ECR_RECV_ENABLE_MASK);
> +       out_be32 (emac.baseaddress + XEM_ECR_OFFSET, helpreg);
> +
> +       if (!getenv("ethaddr")) {
> +               memcpy(bis->bi_enetaddr, emacaddr, ENET_ADDR_LENGTH);
> +       }
> +
> +       /* Set the device station address high and low registers */
> +       helpreg = (bis->bi_enetaddr[0] << 8) | bis->bi_enetaddr[1];
> +       out_be32 (emac.baseaddress + XEM_SAH_OFFSET, helpreg);
> +       helpreg = (bis->bi_enetaddr[2] << 24) | (bis->bi_enetaddr[3] << 16) |
> +                       (bis->bi_enetaddr[4] << 8) | bis->bi_enetaddr[5];
> +       out_be32 (emac.baseaddress + XEM_SAL_OFFSET, helpreg);
> +
> +
> +       helpreg = XEM_ECR_UNICAST_ENABLE_MASK | XEM_ECR_BROAD_ENABLE_MASK |
> +               XEM_ECR_FULL_DUPLEX_MASK | XEM_ECR_XMIT_FCS_ENABLE_MASK |
> +               XEM_ECR_XMIT_PAD_ENABLE_MASK | XEM_ECR_PHY_ENABLE_MASK;
> +       out_be32 (emac.baseaddress + XEM_ECR_OFFSET, helpreg);
> +
> +       emac.isstarted = 1;
> +
> +       /* Enable the transmitter, and receiver */
> +       helpreg = in_be32 (emac.baseaddress + XEM_ECR_OFFSET);
> +       helpreg &= ~(XEM_ECR_XMIT_RESET_MASK | XEM_ECR_RECV_RESET_MASK);
> +       helpreg |= (XEM_ECR_XMIT_ENABLE_MASK | XEM_ECR_RECV_ENABLE_MASK);
> +       out_be32 (emac.baseaddress + XEM_ECR_OFFSET, helpreg);
> +
> +       printf("EMAC Initialization complete\n\r");
> +       return 0;
> +}
> +
> +int eth_send(volatile void *ptr, int len)
> +{
> +       u32 intrstatus;
> +       u32 xmitstatus;
> +       u32 fifocount;
> +       u32 wordcount;
> +       u32 extrabytecount;
> +       u32 *wordbuffer = (u32 *) ptr;
> +
> +       if (len > ENET_MAX_MTU)
> +               len = ENET_MAX_MTU;
> +
> +       /*
> +        * Check for overruns and underruns for the transmit status and length
> +        * FIFOs and make sure the send packet FIFO is not deadlocked.
> +        * Any of these conditions is bad enough that we do not want to
> +        * continue. The upper layer software should reset the device to resolve+        * the error.
> +        */
> +       intrstatus = in_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET);
> +       if (intrstatus & (XEM_EIR_XMIT_SFIFO_OVER_MASK |
> +                       XEM_EIR_XMIT_LFIFO_OVER_MASK)) {
> +#ifdef DEBUG
> +               puts ("Transmitting overrun error\n");
> +#endif
> +               return 0;
> +       } else if (intrstatus & (XEM_EIR_XMIT_SFIFO_UNDER_MASK |
> +                       XEM_EIR_XMIT_LFIFO_UNDER_MASK)) {
> +#ifdef DEBUG
> +               puts ("Transmitting underrun error\n");
> +#endif
> +               return 0;
> +       } else if (in_be32 (emac.sendfifo.regbaseaddress +
> +                       XPF_COUNT_STATUS_REG_OFFSET) & XPF_DEADLOCK_MASK) {
> +#ifdef DEBUG
> +               puts("Transmitting fifo error\n");
> +#endif
> +               return 0;
> +       }
> +
> +       /*
> +        * Before writing to the data FIFO, make sure the length FIFO is not
> +        * full. The data FIFO might not be full yet even though the length FIFO+        * is. This avoids an overrun condition on the length FIFO and keeps the+        * FIFOs in sync.
> +        *
> +        * Clear the latched LFIFO_FULL bit so next time around the most
> +        * current status is represented
> +        */
> +       if (intrstatus & XEM_EIR_XMIT_LFIFO_FULL_MASK) {
> +               out_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET,
> +                       intrstatus & XEM_EIR_XMIT_LFIFO_FULL_MASK);
> +#ifdef DEBUG
> +               puts ("Fifo is full\n");
> +#endif
> +               return 0;
> +       }
> +
> +       /* get the count of how many words may be inserted into the FIFO */
> +       fifocount = in_be32 (emac.sendfifo.regbaseaddress +
> +                               XPF_COUNT_STATUS_REG_OFFSET) & XPF_COUNT_MASK;
> +       wordcount = len >> 2;
> +       extrabytecount = len & 0x3;
> +
> +       if (fifocount < wordcount) {
> +#ifdef DEBUG
> +               puts ("Sending packet is larger then size of FIFO\n");
> +#endif
> +               return 0;
> +       }
> +
> +       for (fifocount = 0; fifocount < wordcount; fifocount++) {
> +               out_be32 (emac.sendfifo.databaseaddress, wordbuffer[fifocount]);+       }
> +       if (extrabytecount > 0) {
> +               u32 lastword = 0;
> +               u8 *extrabytesbuffer = (u8 *) (wordbuffer + wordcount);
> +
> +               if (extrabytecount == 1) {
> +                       lastword = extrabytesbuffer[0] << 24;
> +               } else if (extrabytecount == 2) {
> +                       lastword = extrabytesbuffer[0] << 24 |
> +                               extrabytesbuffer[1] << 16;
> +               } else if (extrabytecount == 3) {
> +                       lastword = extrabytesbuffer[0] << 24 |
> +                               extrabytesbuffer[1] << 16 |
> +                               extrabytesbuffer[2] << 8;
> +               }
> +               out_be32 (emac.sendfifo.databaseaddress, lastword);
> +       }
> +
> +       /* Loop on the MAC's status to wait for any pause to complete */
> +       intrstatus = in_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET);
> +       while ((intrstatus & XEM_EIR_XMIT_PAUSE_MASK) != 0) {
> +               intrstatus = in_be32 ((emac.baseaddress) +
> +                                       XIIF_V123B_IISR_OFFSET);
> +               /* Clear the pause status from the transmit status register */
> +               out_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET,
> +                               intrstatus & XEM_EIR_XMIT_PAUSE_MASK);
> +       }
> +
> +       /*
> +        * Set the MAC's transmit packet length register to tell it to transmit
> +        */
> +       out_be32 (emac.baseaddress + XEM_TPLR_OFFSET, len);
> +
> +       /*
> +        * Loop on the MAC's status to wait for the transmit to complete.
> +        * The transmit status is in the FIFO when the XMIT_DONE bit is set.
> +        */
> +       do {
> +               intrstatus = in_be32 ((emac.baseaddress) +
> +                                               XIIF_V123B_IISR_OFFSET);
> +       }
> +       while ((intrstatus & XEM_EIR_XMIT_DONE_MASK) == 0);
> +
> +       xmitstatus = in_be32 (emac.baseaddress + XEM_TSR_OFFSET);
> +
> +       if (intrstatus & (XEM_EIR_XMIT_SFIFO_OVER_MASK |
> +                                       XEM_EIR_XMIT_LFIFO_OVER_MASK)) {
> +#ifdef DEBUG
> +               puts ("Transmitting overrun error\n");
> +#endif
> +               return 0;
> +       } else if (intrstatus & (XEM_EIR_XMIT_SFIFO_UNDER_MASK |
> +                                       XEM_EIR_XMIT_LFIFO_UNDER_MASK)) {
> +#ifdef DEBUG
> +               puts ("Transmitting underrun error\n");
> +#endif
> +               return 0;
> +       }
> +
> +       /* Clear the interrupt status register of transmit statuses */
> +       out_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET,
> +                               intrstatus & XEM_EIR_XMIT_ALL_MASK);
> +
> +       /*
> +        * Collision errors are stored in the transmit status register
> +        * instead of the interrupt status register
> +        */
> +       if ((xmitstatus & XEM_TSR_EXCESS_DEFERRAL_MASK) ||
> +                               (xmitstatus & XEM_TSR_LATE_COLLISION_MASK)) {
> +#ifdef DEBUG
> +               puts ("Transmitting collision error\n");
> +#endif
> +               return 0;
> +       }
> +       return 1;
> +}
> +
> +int eth_rx(void)
> +{
> +       u32 pktlength;
> +       u32 intrstatus;
> +       u32 fifocount;
> +       u32 wordcount;
> +       u32 extrabytecount;
> +       u32 lastword;
> +       u8 *extrabytesbuffer;
> +
> +       if (in_be32 (emac.recvfifo.regbaseaddress + XPF_COUNT_STATUS_REG_OFFSET)+                       & XPF_DEADLOCK_MASK) {
> +               out_be32 (emac.recvfifo.regbaseaddress, XPF_RESET_FIFO_MASK);
> +#ifdef DEBUG
> +               puts ("Receiving FIFO deadlock\n");
> +#endif
> +               return 0;
> +       }
> +
> +       /*
> +        * Get the interrupt status to know what happened (whether an error
> +        * occurred and/or whether frames have been received successfully).
> +        * When clearing the intr status register, clear only statuses that
> +        * pertain to receive.
> +        */
> +       intrstatus = in_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET);
> +       /*
> +        * Before reading from the length FIFO, make sure the length FIFO is not+        * empty. We could cause an underrun error if we try to read from an
> +        * empty FIFO.
> +        */
> +       if (!(intrstatus & XEM_EIR_RECV_DONE_MASK)) {
> +#ifdef DEBUG
> +               /* puts("Receiving FIFO is empty\n"); */
> +#endif
> +               return 0;
> +       }
> +
> +       /*
> +        * Determine, from the MAC, the length of the next packet available
> +        * in the data FIFO (there should be a non-zero length here)
> +        */
> +       pktlength = in_be32 (emac.baseaddress + XEM_RPLR_OFFSET);
> +       if (!pktlength) {
> +               return 0;
> +       }
> +
> +       /*
> +        * Write the RECV_DONE bit in the status register to clear it. This bit
> +        * indicates the RPLR is non-empty, and we know it's set at this point.
> +        * We clear it so that subsequent entry into this routine will reflect
> +        * the current status. This is done because the non-empty bit is latched+        * in the IPIF, which means it may indicate a non-empty condition even
> +        * though there is something in the FIFO.
> +        */
> +       out_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET,
> +                                               XEM_EIR_RECV_DONE_MASK);
> +
> +       fifocount = in_be32 (emac.recvfifo.regbaseaddress +
> +                               XPF_COUNT_STATUS_REG_OFFSET) & XPF_COUNT_MASK;
> +
> +       if ((fifocount * 4) < pktlength) {
> +#ifdef DEBUG
> +               puts ("Receiving FIFO is smaller than packet size.\n");
> +#endif
> +               return 0;
> +       }
> +
> +       wordcount = pktlength >> 2;
> +       extrabytecount = pktlength & 0x3;
> +
> +       for (fifocount = 0; fifocount < wordcount; fifocount++) {
> +               etherrxbuff[fifocount] =
> +                               in_be32 (emac.recvfifo.databaseaddress);
> +       }
> +
> +       /*
> +        * if there are extra bytes to handle, read the last word from the FIFO
> +        * and insert the extra bytes into the buffer
> +        */
> +       if (extrabytecount > 0) {
> +               extrabytesbuffer = (u8 *) (etherrxbuff + wordcount);
> +
> +               lastword = in_be32 (emac.recvfifo.databaseaddress);
> +
> +               /*
> +                * one extra byte in the last word, put the byte into the next
> +                * location of the buffer, bytes in a word of the FIFO are
> +                * ordered from most significant byte to least
> +                */
> +               if (extrabytecount == 1) {
> +                       extrabytesbuffer[0] = (u8) (lastword >> 24);
> +               } else if (extrabytecount == 2) {
> +                       extrabytesbuffer[0] = (u8) (lastword >> 24);
> +                       extrabytesbuffer[1] = (u8) (lastword >> 16);
> +               } else if (extrabytecount == 3) {
> +                       extrabytesbuffer[0] = (u8) (lastword >> 24);
> +                       extrabytesbuffer[1] = (u8) (lastword >> 16);
> +                       extrabytesbuffer[2] = (u8) (lastword >> 8);
> +               }
> +       }
> +       NetReceive((uchar *)etherrxbuff, pktlength);
> +       return 1;
> +}
> +#endif
> diff --git a/drivers/net/xilinx_emac.h b/drivers/net/xilinx_emac.h
> new file mode 100644
> index 0000000..966598e
> --- /dev/null
> +++ b/drivers/net/xilinx_emac.h

This isn't used anywhere but xilinx_emac.c.  I'd just roll them into
the same file.


-- 
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.
grant.likely at secretlab.ca
(403) 399-0195

[U-Boot-Users] [PATCH9] microblaze EMAC support

[Michal Simek]

> DESC: Xilinx Emac support
>
> Signed-off-by: Michal Simek <monstr@monstr.eu>

> Another good looking driver.  All my comments are minor ones.
:-)

>This isn't used anywhere but xilinx_emac.c.  I'd just roll them into
>the same file.
It's question for Wolfgang instead of me. Could you comment it? What is the better way?

M

[U-Boot-Users] [PATCH9] microblaze EMAC support

[Wolfgang Denk]

In message <2111.4027-22284-1365301341-1189525568@seznam.cz> you wrote:
> > DESC: Xilinx Emac support
> >
> > Signed-off-by: Michal Simek <monstr@monstr.eu>
> 
> > Another good looking driver.  All my comments are minor ones.
> :-)
> 
> >This isn't used anywhere but xilinx_emac.c.  I'd just roll them into
> >the same file.
> It's question for Wolfgang instead of me. Could you comment it? What is the better way?

I don't know how likely it is that this code might ever  be  used  by
some  other  sources, so factoring out makes sense. If it's unlikely,
then roll it into one.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
It is undignified for a woman to play servant to a man who is not
hers.
	-- Spock, "Amok Time", stardate 3372.7

[U-Boot-Users] [PATCH9] microblaze EMAC support

[Grant Likely]

On 8/30/07, Michal Simek <Monstr@seznam.cz> wrote:
> DESC: Xilinx Emac support
>
> Signed-off-by: Michal Simek <monstr@monstr.eu>
>
> Note: driver is tested for Microblaze CPU. Please test it for PowerPC405 and then remove code
>
> diff --git a/drivers/net/xilinx_emac.c b/drivers/net/xilinx_emac.c
> new file mode 100644
> index 0000000..36e627a
> --- /dev/null
> +++ b/drivers/net/xilinx_emac.c
> @@ -0,0 +1,374 @@
> +/*
> + * (C) Copyright 2007 Michal Simek
> + *
> + * Michal SIMEK <monstr@monstr.eu>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + *
> + * Based on Xilinx drivers

Is this based on, as in "used the xilinx driver as a reference", or as
in "started with the xilinx code and modified it".  It you started
with the xilinx code, then you need to preserve Xilinx's original
copyright message and license text verbatim in addition to your
copyright/license text.

> + *
> + */

-- 
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.
grant.likely at secretlab.ca
(403) 399-0195

[U-Boot-Users] [PATCH9] microblaze EMAC support

[Michal Simek]

> + * Based on Xilinx drivers

>Is this based on, as in "used the xilinx driver as a reference", or as
>in "started with the xilinx code and modified it".  It you started
>with the xilinx code, then you need to preserve Xilinx's original
>copyright message and license text verbatim in addition to your
>copyright/license text.

I am newbie in this licencing problem. The conslusion is that I add only one line to current licence as you wrote or I must add the whole xilinx licence with information about my person?

thanks
Michal

Re: FDT for Microblaze and PPC405

[Grant Likely]

On 9/11/07, Michal Simek <Monstr@seznam.cz> wrote:
> Hi Grant,

(Adding linuxppc-dev mailing list to CC list because we're discussing
FDT issues)

> I made EDK repository file for generation dts file from Xilinx design. I sent it to Wolfgang and Steve this week.
> It is in the same config file as I use for configuration Microblaze for U-BOOT. If you want I can send you this repository files.

Yes, please do.

> And I start with redesigning Linux kernel for Microblaze. I ported some peripherals as timer and intc etc.
> But for some peripherals I need better configuration.
>
> I have no time to read information about fdt. Can you tell me what labels I can use?

Steve has already done a bunch of work in this direction on
microblaze, I would converse with him.

>
> For example emaclite driver needs information about turning on/off ping pong buffer...
>
> I would like to make this properly.

FDT design is just as much art as it is science.  It takes taste and
judgement to desgin a nice set of bindings.  Your best option is to
draft something and post it to the linuxppc-embedded mailing list for
review.

>
> And second question is on early console logs and timers setting. I read about aliases in FDT. I think that aliases can cover this setting.
> For example my design contain 4 serial line and I would like to know which serial line is set on early console.

You use the chosen node for this.  In the chosen node, you add a
property called "linux,stdout-path" which holds the path to your
console.  You can look at examples under arch/powerpc/boot/dts/*

Cheers,
g.


-- 
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.
grant.likely@secretlab.ca
(403) 399-0195

Re: FDT for Microblaze and PPC405

[David Gibson]

On Tue, Sep 11, 2007 at 11:09:07AM -0600, Grant Likely wrote:
> On 9/11/07, Michal Simek <Monstr@seznam.cz> wrote:
> > For example emaclite driver needs information about turning on/off ping pong buffer...
> >
> > I would like to make this properly.
> 
> FDT design is just as much art as it is science.  It takes taste and
> judgement to desgin a nice set of bindings.  Your best option is to
> draft something and post it to the linuxppc-embedded mailing list for
> review.

Yes, this is the preferred procedure, for now.

> > And second question is on early console logs and timers setting. I read about aliases in FDT. I think that aliases can cover this setting.
> > For example my design contain 4 serial line and I would like to know which serial line is set on early console.
> 
> You use the chosen node for this.  In the chosen node, you add a
> property called "linux,stdout-path" which holds the path to your
> console.  You can look at examples under arch/powerpc/boot/dts/*

Yes.  Currently we don't use /aliases in the flat device tree.  This
is possibly a mistake, and something I'm thinking about changing.
But, for now, linux,stdout-path in /chosen is the way to do this.

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

Re: FDT for Microblaze and PPC405

[Michal Simek]

Hi David and Grant

>> > For example emaclite driver needs information about turning on/off ping pong
buffer...
>> >
>> > I would like to make this properly.
>>
>> FDT design is just as much art as it is science.  It takes taste and
>> judgement to desgin a nice set of bindings.  Your best option is to
>> draft something and post it to the linuxppc-embedded mailing list for
>> review.
>
>Yes, this is the preferred procedure, for now.

OK. Science is good for me because I am looking for theme for dissertation thesis
and FPGA based FDT can be good choice.

>> > And second question is on early console logs and timers setting. I read
>about aliases in FDT. I think that aliases can cover this setting.
>> > For example my design contain 4 serial line and I would like to know which
>serial line is set on early console.
>>
>> You use the chosen node for this.  In the chosen node, you add a
>> property called "linux,stdout-path" which holds the path to your
>> console.  You can look at examples under arch/powerpc/boot/dts/*

>Yes.  Currently we don't use /aliases in the flat device tree.  This
>is possibly a mistake, and something I'm thinking about changing.
>But, for now, linux,stdout-path in /chosen is the way to do this.

OK. I will make the first draft and send it to list for review but it will be
only part of patch rely on with ppc405 because we don't have microblaze kernel code.

Michal Simek

Re: FDT for Microblaze and PPC405

[Michal Simek]

Hi,
I made EDK tcl script for generation DTS test scructure for FDT. Script 
support Microblaze and PowerPC 405.
Script was primary built for generation U-BOOT configs files for Microblaze.
For Microblaze can you generate both files (FDT and U-BOOT).
For PowerPC can you generate only DTS file. Generation U-BOOT configs files 
aren't supported yet. Script ends after generation DTS.
Script has 2.00.a mark.
It is available at www.monstr.eu.

Cheers,
Michal Simek


> On 9/11/07, Michal Simek <Monstr@seznam.cz> wrote:
>> Hi Grant,
>
> (Adding linuxppc-dev mailing list to CC list because we're discussing
> FDT issues)
>
>> I made EDK repository file for generation dts file from Xilinx design. I 
>> sent it to Wolfgang and Steve this week.
>> It is in the same config file as I use for configuration Microblaze for 
>> U-BOOT. If you want I can send you this repository files.
>
> Yes, please do.
>
>> And I start with redesigning Linux kernel for Microblaze. I ported some 
>> peripherals as timer and intc etc.
>> But for some peripherals I need better configuration.
>>
>> I have no time to read information about fdt. Can you tell me what labels 
>> I can use?
>
> Steve has already done a bunch of work in this direction on
> microblaze, I would converse with him.
>
>>
>> For example emaclite driver needs information about turning on/off ping 
>> pong buffer...
>>
>> I would like to make this properly.
>
> FDT design is just as much art as it is science.  It takes taste and
> judgement to desgin a nice set of bindings.  Your best option is to
> draft something and post it to the linuxppc-embedded mailing list for
> review.
>
>>
>> And second question is on early console logs and timers setting. I read 
>> about aliases in FDT. I think that aliases can cover this setting.
>> For example my design contain 4 serial line and I would like to know 
>> which serial line is set on early console.
>
> You use the chosen node for this.  In the chosen node, you add a
> property called "linux,stdout-path" which holds the path to your
> console.  You can look at examples under arch/powerpc/boot/dts/*
>
> Cheers,
> g.
>
>
> -- 
> Grant Likely, B.Sc., P.Eng.
> Secret Lab Technologies Ltd.
> grant.likely@secretlab.ca
> (403) 399-0195
>
>
> -- 
> No virus found in this incoming message.
> Checked by AVG Free Edition.
> Version: 7.5.485 / Virus Database: 269.13.15/1002 - Release Date: 
> 11.9.2007 05:46
>
>