* [PATCH] [QEMU-DM] Upgrade emulated UART to 16550A.
@ 2007-12-04 16:32 Trolle Selander
2007-12-04 16:48 ` Alan Cox
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Trolle Selander @ 2007-12-04 16:32 UTC (permalink / raw)
To: xen-devel
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This patch adds 16550 emulation to qemu-dm. I still consider it a work in
progress, but from my testing, it consistently performs better than the old
code already, sometimes considerably so (on my laptop, dumping out data over
serial from a HVM DomU -> pty in Dom0 was up to 5.3 times faster than with
the old 16450 code). I can consistenly reach full 115200 baud speeds over
physical serial lines when the virtual device is backed by a phys port,
which I never could with the old code.
There are still some things to be done. I want to add proper error handling,
so that overflow/framing & parity errors on the physical port get detected
and reported by the virtual port. Also, now that FIFOs are in place, I
believe performance could be improved significantly by putting some code
into the hypervisor so that reads & writes from the FIFOs don't have to exit
into qemu-dm at all. I'm also reading up on the specs for newer uarts with
deeper FIFOs.
However, for now, I think this patch is already quite good, and I don't
think I should sit on it any longer. I'm looking forward to hearing what
results others will get with it.
It applies on top of my previously posted patch for modem status/control
line passthrough, so I'm re-posting that patch here as well to make things
easier.
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[-- Attachment #2: xen-qemudm-modemcontrol.patch --]
[-- Type: text/x-patch; name=xen-qemudm-modemcontrol.patch, Size: 9884 bytes --]
diff -uNr xen-unstable.hg-orig/tools/ioemu/hw/serial.c xen-unstable.hg-mc/tools/ioemu/hw/serial.c
--- xen-unstable.hg-orig/tools/ioemu/hw/serial.c 2007-11-15 10:38:45.000000000 -0800
+++ xen-unstable.hg-mc/tools/ioemu/hw/serial.c 2007-11-16 10:33:46.000000000 -0800
@@ -25,6 +25,7 @@
#include <sys/time.h>
#include <time.h>
#include <assert.h>
+#include <asm/termios.h>
//#define DEBUG_SERIAL
@@ -63,7 +64,7 @@
#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
#define UART_MSR_DDSR 0x02 /* Delta DSR */
#define UART_MSR_DCTS 0x01 /* Delta CTS */
-#define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
+#define UART_MSR_ANY_DELTA 0x0F /* Any of the msr delta bits */
#define UART_LSR_TEMT 0x40 /* Transmitter empty */
#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
@@ -72,6 +73,7 @@
#define UART_LSR_PE 0x04 /* Parity error indicator */
#define UART_LSR_OE 0x02 /* Overrun error indicator */
#define UART_LSR_DR 0x01 /* Receiver data ready */
+#define UART_LSR_INT_ANY 0x1E /* Any of the lsr-interrupt-triggering status bits */
/* Maximum retries for a single byte transmit. */
#define WRITE_MAX_SINGLE_RETRIES 3
@@ -98,6 +100,8 @@
int last_break_enable;
target_ulong base;
int it_shift;
+ uint64_t char_transmit_time; /* time to transmit a char in ticks*/
+ int poll_msl;
/*
* If a character transmitted via UART cannot be written to its
@@ -111,18 +115,31 @@
int write_total_retries;
char write_chr;
QEMUTimer *write_retry_timer;
+ QEMUTimer *modem_status_poll;
};
static void serial_update_irq(SerialState *s)
{
- if ((s->lsr & UART_LSR_DR) && (s->ier & UART_IER_RDI)) {
- s->iir = UART_IIR_RDI;
- } else if (s->thr_ipending && (s->ier & UART_IER_THRI)) {
- s->iir = UART_IIR_THRI;
- } else {
- s->iir = UART_IIR_NO_INT;
+ uint8_t tmp_iir = UART_IIR_NO_INT;
+
+ if (!s->ier) {
+ s->set_irq(s->irq_opaque, s->irq, 0);
+ return;
}
- if (s->iir != UART_IIR_NO_INT) {
+
+ if ( ( s->ier & UART_IER_RLSI ) && ( s->lsr & UART_LSR_INT_ANY ) ) {
+ tmp_iir = UART_IIR_RLSI;
+ } else if ( ( s->ier & UART_IER_RDI ) && ( s->lsr & UART_LSR_DR ) ) {
+ tmp_iir = UART_IIR_RDI;
+ } else if ( ( s->ier & UART_IER_THRI ) && s->thr_ipending ) {
+ tmp_iir = UART_IIR_THRI;
+ } else if ( ( s->ier & UART_IER_MSI ) && ( s->msr & UART_MSR_ANY_DELTA ) ) {
+ tmp_iir = UART_IIR_MSI;
+ }
+
+ s->iir = tmp_iir | ( s->iir & 0xF0 );
+
+ if ( tmp_iir != UART_IIR_NO_INT ) {
s->set_irq(s->irq_opaque, s->irq, 1);
} else {
s->set_irq(s->irq_opaque, s->irq, 0);
@@ -131,9 +148,13 @@
static void serial_update_parameters(SerialState *s)
{
- int speed, parity, data_bits, stop_bits;
+ int speed, parity, data_bits, stop_bits, frame_size;
QEMUSerialSetParams ssp;
+ if (s->divider == 0)
+ return;
+
+ frame_size = 1;
if (s->lcr & 0x08) {
if (s->lcr & 0x10)
parity = 'E';
@@ -141,19 +162,22 @@
parity = 'O';
} else {
parity = 'N';
+ frame_size = 0;
}
if (s->lcr & 0x04)
stop_bits = 2;
else
stop_bits = 1;
+
data_bits = (s->lcr & 0x03) + 5;
- if (s->divider == 0)
- return;
+ frame_size += data_bits + stop_bits;
+
speed = 115200 / s->divider;
ssp.speed = speed;
ssp.parity = parity;
ssp.data_bits = data_bits;
ssp.stop_bits = stop_bits;
+ s->char_transmit_time = ( ticks_per_sec / speed ) * frame_size;
qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
#if 0
printf("speed=%d parity=%c data=%d stop=%d\n",
@@ -250,6 +274,41 @@
serial_update_irq(s);
}
+static void serial_update_msl( SerialState *s )
+{
+ uint8_t omsr;
+ int flags;
+
+ qemu_del_timer(s->modem_status_poll);
+
+ if ( qemu_chr_ioctl(s->chr,CHR_IOCTL_SERIAL_GET_TIOCM, &flags) == -ENOTSUP ) {
+ s->poll_msl = -1;
+ return;
+ }
+
+ omsr = s->msr;
+
+ s->msr = ( flags & TIOCM_CTS ) ? s->msr | UART_MSR_CTS : s->msr & ~UART_MSR_CTS;
+ s->msr = ( flags & TIOCM_DSR ) ? s->msr | UART_MSR_DSR : s->msr & ~UART_MSR_DSR;
+ s->msr = ( flags & TIOCM_CAR ) ? s->msr | UART_MSR_DCD : s->msr & ~UART_MSR_DCD;
+ s->msr = ( flags & TIOCM_RI ) ? s->msr | UART_MSR_RI : s->msr & ~UART_MSR_RI;
+
+ if ( s->msr != omsr ) {
+ /* Set delta bits */
+ s->msr = s->msr | ( ( s->msr >> 4 ) ^ ( omsr >> 4 ) );
+ /* UART_MSR_TERI only if change was from 1 -> 0 */
+ if ( (s->msr & UART_MSR_TERI) && !(omsr & UART_MSR_RI))
+ s->msr &= ~UART_MSR_TERI;
+ serial_update_irq(s);
+ }
+
+ /* The real 16550A apparently has a 250ns response latency to line status changes.
+ We'll be lazy and poll only every 10ms, and only poll it at all if MSI interrupts are turned on */
+
+ if (s->poll_msl)
+ qemu_mod_timer(s->modem_status_poll, qemu_get_clock(vm_clock) + ticks_per_sec / 100);
+}
+
static void serial_ioport_write(void *opaque, uint32_t addr, uint32_t val)
{
SerialState *s = opaque;
@@ -279,6 +338,17 @@
serial_update_parameters(s);
} else {
s->ier = val & 0x0f;
+ /* Turn on polling of modem status lines if guest has IER_MSI turned on */
+ if ( s->poll_msl >= 0 ) {
+ if ( s->ier & UART_IER_MSI ) {
+ s->poll_msl = 1;
+ serial_update_msl(s);
+ } else {
+ qemu_del_timer(s->modem_status_poll);
+ s->poll_msl = 0;
+ }
+ }
+
if (s->lsr & UART_LSR_THRE) {
s->thr_ipending = 1;
}
@@ -301,7 +371,30 @@
}
break;
case 4:
- s->mcr = val & 0x1f;
+ {
+ int flags;
+ int old_mcr = s->mcr;
+ s->mcr = val & 0x1f;
+ if ( val & UART_MCR_LOOP )
+ break;
+
+ if ( ( s->poll_msl >= 0 ) && ( old_mcr != s->mcr ) ) {
+
+ qemu_chr_ioctl(s->chr,CHR_IOCTL_SERIAL_GET_TIOCM, &flags);
+
+ flags &= ~( TIOCM_RTS | TIOCM_DTR );
+
+ if ( val & UART_MCR_RTS )
+ flags |= TIOCM_RTS;
+ if ( val & UART_MCR_DTR )
+ flags |= TIOCM_DTR;
+
+ qemu_chr_ioctl(s->chr,CHR_IOCTL_SERIAL_SET_TIOCM, &flags);
+
+ /* Update the modem status after a one-character-send wait-time. The dev */
+ qemu_mod_timer(s->modem_status_poll, qemu_get_clock(vm_clock) + s->char_transmit_time );
+ }
+ }
break;
case 5:
break;
@@ -363,7 +456,12 @@
ret |= (s->mcr & 0x02) << 3;
ret |= (s->mcr & 0x01) << 5;
} else {
+ ret = 0;
+ if ( s->poll_msl >= 0 )
+ serial_update_msl(s);
ret = s->msr;
+ s->msr &= 0xF0; /* Clear delta bits after read */
+ serial_update_irq(s);
}
break;
case 7:
@@ -466,10 +564,19 @@
s->set_irq = set_irq;
s->irq_opaque = opaque;
s->irq = irq;
+ s->ier = 0;
s->lsr = UART_LSR_TEMT | UART_LSR_THRE;
s->iir = UART_IIR_NO_INT;
+ s->mcr = UART_MCR_OUT2;
s->msr = UART_MSR_DCD | UART_MSR_DSR | UART_MSR_CTS;
+ /* Default to 9600 baud, no parity, one stop bit */
+ s->divider = 0x0C;
+ s->char_transmit_time = ticks_per_sec * ( 9 / 9600 );
+
s->write_retry_timer = qemu_new_timer(vm_clock, serial_chr_write, s);
+ s->modem_status_poll = qemu_new_timer(vm_clock, serial_update_msl, s);
+
+ s->poll_msl = 0;
register_savevm("serial", base, 2, serial_save, serial_load, s);
@@ -478,6 +585,8 @@
s->chr = chr;
qemu_chr_add_handlers(chr, serial_can_receive1, serial_receive1,
serial_event, s);
+ serial_update_msl(s);
+
return s;
}
@@ -552,12 +661,21 @@
s->set_irq = set_irq;
s->irq_opaque = opaque;
s->irq = irq;
+ s->ier = 0;
s->lsr = UART_LSR_TEMT | UART_LSR_THRE;
s->iir = UART_IIR_NO_INT;
+ s->mcr = UART_MCR_OUT2;
s->msr = UART_MSR_DCD | UART_MSR_DSR | UART_MSR_CTS;
+ /* Default to 9600 baud, no parity, one stop bit */
+ s->divider = 0x0C;
+ s->char_transmit_time = ticks_per_sec * ( 9 / 9600 );
+
s->base = base;
s->it_shift = it_shift;
+
s->write_retry_timer = qemu_new_timer(vm_clock, serial_chr_write, s);
+ s->modem_status_poll = qemu_new_timer(vm_clock, serial_update_msl, s);
+ s->poll_msl = 0;
register_savevm("serial", base, 2, serial_save, serial_load, s);
diff -uNr xen-unstable.hg-orig/tools/ioemu/vl.c xen-unstable.hg-mc/tools/ioemu/vl.c
--- xen-unstable.hg-orig/tools/ioemu/vl.c 2007-11-15 10:38:45.000000000 -0800
+++ xen-unstable.hg-mc/tools/ioemu/vl.c 2007-11-16 10:33:04.000000000 -0800
@@ -1932,6 +1932,16 @@
tcsendbreak(s->fd_in, 1);
}
break;
+ case CHR_IOCTL_SERIAL_GET_TIOCM:
+ {
+ ioctl(s->fd_in, TIOCMGET, arg);
+ }
+ break;
+ case CHR_IOCTL_SERIAL_SET_TIOCM:
+ {
+ ioctl(s->fd_in, TIOCMSET, arg);
+ }
+ break;
default:
return -ENOTSUP;
}
diff -uNr xen-unstable.hg-orig/tools/ioemu/vl.h xen-unstable.hg-mc/tools/ioemu/vl.h
--- xen-unstable.hg-orig/tools/ioemu/vl.h 2007-11-15 10:38:45.000000000 -0800
+++ xen-unstable.hg-mc/tools/ioemu/vl.h 2007-11-15 11:13:28.000000000 -0800
@@ -317,6 +317,10 @@
#define CHR_IOCTL_PP_WRITE_CONTROL 6
#define CHR_IOCTL_PP_READ_STATUS 7
+
+#define CHR_IOCTL_SERIAL_SET_TIOCM 8
+#define CHR_IOCTL_SERIAL_GET_TIOCM 9
+
typedef void IOEventHandler(void *opaque, int event);
typedef struct CharDriverState {
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[-- Attachment #3: xen-qemudm-16550.patch --]
[-- Type: text/x-patch; name=xen-qemudm-16550.patch, Size: 22465 bytes --]
diff -uNr xen-unstable.hg-patched/tools/ioemu/hw/serial.c xen-unstable.hg-patched2/tools/ioemu/hw/serial.c
--- xen-unstable.hg-patched/tools/ioemu/hw/serial.c 2007-12-04 15:24:33.000000000 +0100
+++ xen-unstable.hg-patched2/tools/ioemu/hw/serial.c 2007-12-04 15:37:38.000000000 +0100
@@ -1,5 +1,5 @@
/*
- * QEMU 16450 UART emulation
+ * QEMU 16550A UART emulation
*
* Copyright (c) 2003-2004 Fabrice Bellard
*
@@ -21,6 +21,7 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
+
#include "vl.h"
#include <sys/time.h>
#include <time.h>
@@ -43,6 +44,10 @@
#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
#define UART_IIR_RDI 0x04 /* Receiver data interrupt */
#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
+#define UART_IIR_CTI 0x0C /* Character Timeout Indication */
+
+#define UART_IIR_FENF 0x80 /* Fifo enabled, but not functionning */
+#define UART_IIR_FE 0xC0 /* Fifo enabled */
/*
* These are the definitions for the Modem Control Register
@@ -75,14 +80,36 @@
#define UART_LSR_DR 0x01 /* Receiver data ready */
#define UART_LSR_INT_ANY 0x1E /* Any of the lsr-interrupt-triggering status bits */
-/* Maximum retries for a single byte transmit. */
-#define WRITE_MAX_SINGLE_RETRIES 3
-/* Maximum retries for a sequence of back-to-back unsuccessful transmits. */
-#define WRITE_MAX_TOTAL_RETRIES 10
+/* Interrupt trigger levels. The byte-counts are for 16550A - in newer UARTs the byte-count for each ITL is higher. */
+
+#define UART_FCR_ITL_1 0x00 /* 1 byte ITL */
+#define UART_FCR_ITL_2 0x40 /* 4 bytes ITL */
+#define UART_FCR_ITL_3 0x80 /* 8 bytes ITL */
+#define UART_FCR_ITL_4 0xC0 /* 14 bytes ITL */
+
+#define UART_FCR_DMS 0x08 /* DMA Mode Select */
+#define UART_FCR_XFR 0x04 /* XMIT Fifo Reset */
+#define UART_FCR_RFR 0x02 /* RCVR Fifo Reset */
+#define UART_FCR_FE 0x01 /* FIFO Enable */
+
+#define UART_FIFO_LENGTH 16 /* 16550A Fifo Length */
+
+#define XMIT_FIFO 0
+#define RECV_FIFO 1
+
+struct SerialFIFO {
+ uint8_t data[UART_FIFO_LENGTH];
+ uint8_t count;
+ uint8_t itl; /* Interrupt Trigger Level */
+ uint8_t tail;
+ uint8_t head;
+} typedef SerialFIFO;
struct SerialState {
uint16_t divider;
uint8_t rbr; /* receive register */
+ uint8_t thr; /* transmit holding register */
+ uint8_t tsr; /* transmit shift register */
uint8_t ier;
uint8_t iir; /* read only */
uint8_t lcr;
@@ -90,6 +117,7 @@
uint8_t lsr; /* read only */
uint8_t msr; /* read only */
uint8_t scr;
+ uint8_t fcr;
/* NOTE: this hidden state is necessary for tx irq generation as
it can be reset while reading iir */
int thr_ipending;
@@ -100,24 +128,73 @@
int last_break_enable;
target_ulong base;
int it_shift;
+ int tsr_retry;
+
+ uint64_t last_xmit_ts; /* Time when the last byte was successfully sent out of the tsr */
+ SerialFIFO recv_fifo;
+ SerialFIFO xmit_fifo;
+
+ struct QEMUTimer *fifo_timeout_timer;
+ int timeout_ipending; /* timeout interrupt pending state */
+ struct QEMUTimer *fifo_transmit_timer;
+
+
uint64_t char_transmit_time; /* time to transmit a char in ticks*/
int poll_msl;
- /*
- * If a character transmitted via UART cannot be written to its
- * destination immediately we remember it here and retry a few times via
- * a polling timer.
- * - write_single_retries: Number of write retries for current byte.
- * - write_total_retries: Number of write retries for back-to-back
- * unsuccessful transmits.
- */
- int write_single_retries;
- int write_total_retries;
- char write_chr;
- QEMUTimer *write_retry_timer;
- QEMUTimer *modem_status_poll;
+ struct QEMUTimer *modem_status_poll;
};
+/* Rate limit serial requests so that e.g. grub on a serial console
+ doesn't kill dom0. Simple token bucket. If we get some actual
+ data from the user, instantly refil the bucket. */
+
+/* How long it takes to generate a token, in microseconds. */
+#define TOKEN_PERIOD 1000
+/* Maximum and initial size of token bucket */
+#define TOKENS_MAX 100000
+
+static int tokens_avail;
+
+static void fifo_clear(SerialState *s, int fifo) {
+ SerialFIFO *f = ( fifo ) ? &s->recv_fifo : &s->xmit_fifo;
+ memset(f->data, 0, UART_FIFO_LENGTH);
+ f->count = 0;
+ f->head = 0;
+ f->tail = 0;
+}
+
+static int fifo_put(SerialState *s, int fifo, uint8_t chr) {
+ SerialFIFO *f = ( fifo ) ? &s->recv_fifo : &s->xmit_fifo;
+
+ f->data[f->head++] = chr;
+
+ if (f->head == UART_FIFO_LENGTH)
+ f->head = 0;
+ f->count++;
+
+ tokens_avail = TOKENS_MAX;
+
+ return 1;
+}
+
+uint8_t fifo_get(SerialState *s, int fifo) {
+ SerialFIFO *f = ( fifo ) ? &s->recv_fifo : &s->xmit_fifo;
+ uint8_t c;
+
+ if( f->count == 0 )
+ return 0;
+
+ c = f->data[f->tail++];
+ if (f->tail == UART_FIFO_LENGTH)
+ f->tail = 0;
+ f->count--;
+
+ tokens_avail = TOKENS_MAX;
+
+ return c;
+}
+
static void serial_update_irq(SerialState *s)
{
uint8_t tmp_iir = UART_IIR_NO_INT;
@@ -127,13 +204,19 @@
return;
}
- if ( ( s->ier & UART_IER_RLSI ) && ( s->lsr & UART_LSR_INT_ANY ) ) {
+ if ( ( s->ier & UART_IER_RLSI ) && (s->lsr & UART_LSR_INT_ANY ) ) {
tmp_iir = UART_IIR_RLSI;
- } else if ( ( s->ier & UART_IER_RDI ) && ( s->lsr & UART_LSR_DR ) ) {
- tmp_iir = UART_IIR_RDI;
- } else if ( ( s->ier & UART_IER_THRI ) && s->thr_ipending ) {
- tmp_iir = UART_IIR_THRI;
- } else if ( ( s->ier & UART_IER_MSI ) && ( s->msr & UART_MSR_ANY_DELTA ) ) {
+ } else if ( s->timeout_ipending ) {
+ tmp_iir = UART_IIR_CTI;
+ } else if ( ( s->ier & UART_IER_RDI ) && (s->lsr & UART_LSR_DR ) ) {
+ if ( !(s->iir & UART_FCR_FE) ) {
+ tmp_iir = UART_IIR_RDI;
+ } else if ( s->recv_fifo.count >= s->recv_fifo.itl ) {
+ tmp_iir = UART_IIR_RDI;
+ }
+ } else if ( (s->ier & UART_IER_THRI) && s->thr_ipending ) {
+ tmp_iir = UART_IIR_THRI;
+ } else if ( (s->ier & UART_IER_MSI) && (s->msr & UART_MSR_ANY_DELTA) ) {
tmp_iir = UART_IIR_MSI;
}
@@ -185,17 +268,6 @@
#endif
}
-/* Rate limit serial requests so that e.g. grub on a serial console
- doesn't kill dom0. Simple token bucket. If we get some actual
- data from the user, instantly refil the bucket. */
-
-/* How long it takes to generate a token, in microseconds. */
-#define TOKEN_PERIOD 1000
-/* Maximum and initial size of token bucket */
-#define TOKENS_MAX 100000
-
-static int tokens_avail;
-
static void serial_get_token(void)
{
static struct timeval last_refil_time;
@@ -246,34 +318,6 @@
tokens_avail--;
}
-static void serial_chr_write(void *opaque)
-{
- SerialState *s = opaque;
-
- /* Cancel any outstanding retry if this is a new byte. */
- qemu_del_timer(s->write_retry_timer);
-
- /* Retry every 100ms for 300ms total. */
- if (qemu_chr_write(s->chr, &s->write_chr, 1) == -1) {
- s->write_total_retries++;
- if (s->write_single_retries++ >= WRITE_MAX_SINGLE_RETRIES)
- fprintf(stderr, "serial: write error\n");
- else if (s->write_total_retries <= WRITE_MAX_TOTAL_RETRIES) {
- qemu_mod_timer(s->write_retry_timer,
- qemu_get_clock(vm_clock) + ticks_per_sec / 10);
- return;
- }
- } else {
- s->write_total_retries = 0; /* if successful then reset counter */
- }
-
- /* Success: Notify guest that THR is empty. */
- s->thr_ipending = 1;
- s->lsr |= UART_LSR_THRE;
- s->lsr |= UART_LSR_TEMT;
- serial_update_irq(s);
-}
-
static void serial_update_msl( SerialState *s )
{
uint8_t omsr;
@@ -285,7 +329,7 @@
s->poll_msl = -1;
return;
}
-
+
omsr = s->msr;
s->msr = ( flags & TIOCM_CTS ) ? s->msr | UART_MSR_CTS : s->msr & ~UART_MSR_CTS;
@@ -297,7 +341,7 @@
/* Set delta bits */
s->msr = s->msr | ( ( s->msr >> 4 ) ^ ( omsr >> 4 ) );
/* UART_MSR_TERI only if change was from 1 -> 0 */
- if ( (s->msr & UART_MSR_TERI) && !(omsr & UART_MSR_RI))
+ if ( ( s->msr & UART_MSR_TERI ) && !( omsr & UART_MSR_RI ) )
s->msr &= ~UART_MSR_TERI;
serial_update_irq(s);
}
@@ -305,10 +349,45 @@
/* The real 16550A apparently has a 250ns response latency to line status changes.
We'll be lazy and poll only every 10ms, and only poll it at all if MSI interrupts are turned on */
- if (s->poll_msl)
+ if ( s->poll_msl )
qemu_mod_timer(s->modem_status_poll, qemu_get_clock(vm_clock) + ticks_per_sec / 100);
}
+static void serial_xmit(void *opaque) {
+ SerialState *s = opaque;
+ uint64_t new_xmit_ts = qemu_get_clock(vm_clock);
+
+ if ( s->tsr_retry == 0 ) {
+ if (s->fcr & UART_FCR_FE) {
+ s->tsr = fifo_get(s,XMIT_FIFO);
+ if ( !s->xmit_fifo.count )
+ s->lsr |= UART_LSR_THRE;
+ } else {
+ s->tsr = s->thr;
+ s->lsr |= UART_LSR_THRE;
+ }
+ }
+
+ if ( qemu_chr_write(s->chr, &s->tsr, 1) != 1 ) {
+ s->tsr_retry++;
+ qemu_mod_timer(s->fifo_transmit_timer, new_xmit_ts + s->char_transmit_time );
+ return;
+ }
+
+ s->tsr_retry = 0;
+ s->last_xmit_ts = qemu_get_clock(vm_clock);
+
+ if ( s->xmit_fifo.count > 0 )
+ qemu_mod_timer(s->fifo_transmit_timer, s->last_xmit_ts + s->char_transmit_time );
+
+ if ( s->lsr & UART_LSR_THRE ) {
+ s->lsr |= UART_LSR_TEMT;
+ s->thr_ipending = 1;
+ serial_update_irq(s);
+ }
+}
+
+
static void serial_ioport_write(void *opaque, uint32_t addr, uint32_t val)
{
SerialState *s = opaque;
@@ -324,12 +403,19 @@
s->divider = (s->divider & 0xff00) | val;
serial_update_parameters(s);
} else {
- s->thr_ipending = 0;
- s->lsr &= ~UART_LSR_THRE;
- serial_update_irq(s);
- s->write_chr = val;
- s->write_single_retries = 0;
- serial_chr_write(s);
+ s->thr = (uint8_t) val;
+ if(s->fcr & UART_FCR_FE) {
+ fifo_put(s, XMIT_FIFO, s->thr);
+ s->thr_ipending = 0;
+ s->lsr &= ~UART_LSR_TEMT;
+ s->lsr &= ~UART_LSR_THRE;
+ serial_update_irq(s);
+ } else {
+ s->thr_ipending = 0;
+ s->lsr &= ~UART_LSR_THRE;
+ serial_update_irq(s);
+ }
+ serial_xmit(s);
}
break;
case 1:
@@ -338,7 +424,8 @@
serial_update_parameters(s);
} else {
s->ier = val & 0x0f;
- /* Turn on polling of modem status lines if guest has IER_MSI turned on */
+ /* If the backend device is a real serial port, turn polling of the modem
+ status lines on physical port on or off depending on UART_IER_MSI state */
if ( s->poll_msl >= 0 ) {
if ( s->ier & UART_IER_MSI ) {
s->poll_msl = 1;
@@ -348,14 +435,57 @@
s->poll_msl = 0;
}
}
-
if (s->lsr & UART_LSR_THRE) {
s->thr_ipending = 1;
+ serial_update_irq(s);
}
- serial_update_irq(s);
}
break;
case 2:
+ val = val & 0xFF;
+
+ if ( s->fcr == val)
+ break;
+
+ /* Did the enable/disable flag change? If so, make sure FIFOs get flushed */
+ if ( (val ^ s->fcr) & UART_FCR_FE )
+ val |= UART_FCR_XFR | UART_FCR_RFR;
+
+ /* FIFO clear */
+
+ if ( val & UART_FCR_RFR ) {
+ qemu_del_timer(s->fifo_timeout_timer);
+ s->timeout_ipending=0;
+ fifo_clear(s,RECV_FIFO);
+ }
+
+ if ( val & UART_FCR_XFR ) {
+ fifo_clear(s,XMIT_FIFO);
+ }
+
+ if ( val & UART_FCR_FE ) {
+ s->iir |= UART_IIR_FE;
+ /* Set RECV_FIFO trigger Level */
+ switch ( val & 0xC0 ) {
+ case UART_FCR_ITL_1:
+ s->recv_fifo.itl = 1;
+ break;
+ case UART_FCR_ITL_2:
+ s->recv_fifo.itl = 4;
+ break;
+ case UART_FCR_ITL_3:
+ s->recv_fifo.itl = 8;
+ break;
+ case UART_FCR_ITL_4:
+ s->recv_fifo.itl = 14;
+ break;
+ }
+ } else
+ s->iir &= ~UART_IIR_FE;
+
+ /* Set fcr - or at least the bits in it that are supposed to "stick" */
+ s->fcr = val & 0xC9;
+ serial_update_irq(s);
break;
case 3:
{
@@ -378,7 +508,7 @@
if ( val & UART_MCR_LOOP )
break;
- if ( ( s->poll_msl >= 0 ) && ( old_mcr != s->mcr ) ) {
+ if ( s->poll_msl >= 0 && old_mcr != s->mcr ) {
qemu_chr_ioctl(s->chr,CHR_IOCTL_SERIAL_GET_TIOCM, &flags);
@@ -390,8 +520,8 @@
flags |= TIOCM_DTR;
qemu_chr_ioctl(s->chr,CHR_IOCTL_SERIAL_SET_TIOCM, &flags);
-
- /* Update the modem status after a one-character-send wait-time. The dev */
+ /* Update the modem status after a one-character-send wait-time, since there may be a response
+ from the device/computer at the other end of the serial line */
qemu_mod_timer(s->modem_status_poll, qemu_get_clock(vm_clock) + s->char_transmit_time );
}
}
@@ -418,9 +548,18 @@
if (s->lcr & UART_LCR_DLAB) {
ret = s->divider & 0xff;
} else {
- ret = s->rbr;
- s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);
- serial_update_irq(s);
+ if(s->fcr & UART_FCR_FE) {
+ ret = fifo_get(s,RECV_FIFO);
+ if ( s->recv_fifo.count == 0 )
+ s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);
+ else
+ qemu_mod_timer(s->fifo_timeout_timer, qemu_get_clock (vm_clock) + s->char_transmit_time * 4 );
+ s->timeout_ipending = 0;
+ } else {
+ ret = s->rbr;
+ s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);
+ }
+ serial_update_irq(s);
}
break;
case 1:
@@ -432,9 +571,7 @@
break;
case 2:
ret = s->iir;
- /* reset THR pending bit */
- if ((ret & 0x7) == UART_IIR_THRI)
- s->thr_ipending = 0;
+ s->thr_ipending = 0;
serial_update_irq(s);
break;
case 3:
@@ -446,6 +583,11 @@
case 5:
serial_get_token();
ret = s->lsr;
+ /* Clear break interrupt */
+ if ( s->lsr & UART_LSR_BI ) {
+ s->lsr &= ~UART_LSR_BI;
+ serial_update_irq(s);
+ }
break;
case 6:
serial_get_token();
@@ -456,12 +598,14 @@
ret |= (s->mcr & 0x02) << 3;
ret |= (s->mcr & 0x01) << 5;
} else {
- ret = 0;
if ( s->poll_msl >= 0 )
serial_update_msl(s);
ret = s->msr;
- s->msr &= 0xF0; /* Clear delta bits after read */
- serial_update_irq(s);
+ /* Clear delta bits & msr int after read, if they were set */
+ if ( s->msr & UART_MSR_ANY_DELTA ) {
+ s->msr &= 0xF0;
+ serial_update_irq(s);
+ }
}
break;
case 7:
@@ -476,14 +620,17 @@
static int serial_can_receive(SerialState *s)
{
- return !(s->lsr & UART_LSR_DR);
-}
-
-static void serial_receive_byte(SerialState *s, int ch)
-{
- s->rbr = ch;
- s->lsr |= UART_LSR_DR;
- serial_update_irq(s);
+ if(s->fcr & UART_FCR_FE) {
+ if(s->recv_fifo.count < UART_FIFO_LENGTH)
+ /* Advertise (fifo.itl - fifo.count) bytes when count < ITL, and 1 if above. If UART_FIFO_LENGTH - fifo.count is
+ advertised the effect will be to almost always fill the fifo completely before the guest has a chance to respond,
+ effectively overriding the ITL that the guest has set. */
+ return ( s->recv_fifo.count <= s->recv_fifo.itl ) ? s->recv_fifo.itl - s->recv_fifo.count : 1;
+ else
+ return 0;
+ } else {
+ return !(s->lsr & UART_LSR_DR);
+ }
}
static void serial_receive_break(SerialState *s)
@@ -492,6 +639,15 @@
s->lsr |= UART_LSR_BI | UART_LSR_DR;
serial_update_irq(s);
}
+
+/* There's data in recv_fifo and s->rbr has not been read for 4 char transmit times */
+static void fifo_timeout_int (void *opaque) {
+ SerialState *s = opaque;
+ if ( s->recv_fifo.count ) {
+ s->timeout_ipending = 1;
+ serial_update_irq(s);
+ }
+}
static int serial_can_receive1(void *opaque)
{
@@ -503,7 +659,19 @@
{
SerialState *s = opaque;
tokens_avail = TOKENS_MAX;
- serial_receive_byte(s, buf[0]);
+ if(s->fcr & UART_FCR_FE) {
+ int i;
+ for (i = 0; i < size; i++) {
+ fifo_put(s, RECV_FIFO, buf[i]);
+ }
+ s->lsr |= UART_LSR_DR;
+ /* call the timeout receive callback in 4 char transmit time */
+ qemu_mod_timer(s->fifo_timeout_timer, qemu_get_clock (vm_clock) + s->char_transmit_time * 4);
+ } else {
+ s->rbr = buf[0];
+ s->lsr |= UART_LSR_DR;
+ }
+ serial_update_irq(s);
}
static void serial_event(void *opaque, int event)
@@ -527,6 +695,7 @@
qemu_put_8s(f,&s->lsr);
qemu_put_8s(f,&s->msr);
qemu_put_8s(f,&s->scr);
+ qemu_get_8s(f,&s->fcr);
}
static int serial_load(QEMUFile *f, void *opaque, int version_id)
@@ -548,6 +717,7 @@
qemu_get_8s(f,&s->lsr);
qemu_get_8s(f,&s->msr);
qemu_get_8s(f,&s->scr);
+ qemu_get_8s(f,&s->fcr);
return 0;
}
@@ -571,119 +741,26 @@
s->msr = UART_MSR_DCD | UART_MSR_DSR | UART_MSR_CTS;
/* Default to 9600 baud, no parity, one stop bit */
s->divider = 0x0C;
- s->char_transmit_time = ticks_per_sec * ( 9 / 9600 );
+ s->tsr_retry = 0;
+ s->char_transmit_time = ( ticks_per_sec / 9600 ) * 9;
- s->write_retry_timer = qemu_new_timer(vm_clock, serial_chr_write, s);
- s->modem_status_poll = qemu_new_timer(vm_clock, serial_update_msl, s);
+ s->modem_status_poll = qemu_new_timer(vm_clock, ( QEMUTimerCB *) serial_update_msl, s);
s->poll_msl = 0;
+ fifo_clear(s,RECV_FIFO);
+ fifo_clear(s,XMIT_FIFO);
+ s->last_xmit_ts = qemu_get_clock(vm_clock);
+ s->fifo_timeout_timer = qemu_new_timer(vm_clock, ( QEMUTimerCB *) fifo_timeout_int, s);
+ s->fifo_transmit_timer = qemu_new_timer(vm_clock, ( QEMUTimerCB *) serial_xmit, s);
+
register_savevm("serial", base, 2, serial_save, serial_load, s);
register_ioport_write(base, 8, 1, serial_ioport_write, s);
register_ioport_read(base, 8, 1, serial_ioport_read, s);
s->chr = chr;
- qemu_chr_add_handlers(chr, serial_can_receive1, serial_receive1,
+ qemu_chr_add_handlers(chr, serial_can_receive1, serial_receive1,
serial_event, s);
serial_update_msl(s);
-
- return s;
-}
-
-/* Memory mapped interface */
-static uint32_t serial_mm_readb (void *opaque, target_phys_addr_t addr)
-{
- SerialState *s = opaque;
-
- return serial_ioport_read(s, (addr - s->base) >> s->it_shift) & 0xFF;
-}
-
-static void serial_mm_writeb (void *opaque,
- target_phys_addr_t addr, uint32_t value)
-{
- SerialState *s = opaque;
-
- serial_ioport_write(s, (addr - s->base) >> s->it_shift, value & 0xFF);
-}
-
-static uint32_t serial_mm_readw (void *opaque, target_phys_addr_t addr)
-{
- SerialState *s = opaque;
-
- return serial_ioport_read(s, (addr - s->base) >> s->it_shift) & 0xFFFF;
-}
-
-static void serial_mm_writew (void *opaque,
- target_phys_addr_t addr, uint32_t value)
-{
- SerialState *s = opaque;
-
- serial_ioport_write(s, (addr - s->base) >> s->it_shift, value & 0xFFFF);
-}
-
-static uint32_t serial_mm_readl (void *opaque, target_phys_addr_t addr)
-{
- SerialState *s = opaque;
-
- return serial_ioport_read(s, (addr - s->base) >> s->it_shift);
-}
-
-static void serial_mm_writel (void *opaque,
- target_phys_addr_t addr, uint32_t value)
-{
- SerialState *s = opaque;
-
- serial_ioport_write(s, (addr - s->base) >> s->it_shift, value);
-}
-
-static CPUReadMemoryFunc *serial_mm_read[] = {
- &serial_mm_readb,
- &serial_mm_readw,
- &serial_mm_readl,
-};
-
-static CPUWriteMemoryFunc *serial_mm_write[] = {
- &serial_mm_writeb,
- &serial_mm_writew,
- &serial_mm_writel,
-};
-
-SerialState *serial_mm_init (SetIRQFunc *set_irq, void *opaque,
- target_ulong base, int it_shift,
- int irq, CharDriverState *chr)
-{
- SerialState *s;
- int s_io_memory;
-
- s = qemu_mallocz(sizeof(SerialState));
- if (!s)
- return NULL;
- s->set_irq = set_irq;
- s->irq_opaque = opaque;
- s->irq = irq;
- s->ier = 0;
- s->lsr = UART_LSR_TEMT | UART_LSR_THRE;
- s->iir = UART_IIR_NO_INT;
- s->mcr = UART_MCR_OUT2;
- s->msr = UART_MSR_DCD | UART_MSR_DSR | UART_MSR_CTS;
- /* Default to 9600 baud, no parity, one stop bit */
- s->divider = 0x0C;
- s->char_transmit_time = ticks_per_sec * ( 9 / 9600 );
-
- s->base = base;
- s->it_shift = it_shift;
-
- s->write_retry_timer = qemu_new_timer(vm_clock, serial_chr_write, s);
- s->modem_status_poll = qemu_new_timer(vm_clock, serial_update_msl, s);
- s->poll_msl = 0;
-
- register_savevm("serial", base, 2, serial_save, serial_load, s);
-
- s_io_memory = cpu_register_io_memory(0, serial_mm_read,
- serial_mm_write, s);
- cpu_register_physical_memory(base, 8 << it_shift, s_io_memory);
- s->chr = chr;
- qemu_chr_add_handlers(chr, serial_can_receive1, serial_receive1,
- serial_event, s);
return s;
}
[-- Attachment #4: Type: text/plain, Size: 138 bytes --]
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xensource.com
http://lists.xensource.com/xen-devel
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] [QEMU-DM] Upgrade emulated UART to 16550A.
2007-12-04 16:32 [PATCH] [QEMU-DM] Upgrade emulated UART to 16550A Trolle Selander
@ 2007-12-04 16:48 ` Alan Cox
2007-12-04 18:06 ` Trolle Selander
2007-12-05 13:55 ` Keir Fraser
2007-12-05 14:24 ` Daniel P. Berrange
2 siblings, 1 reply; 6+ messages in thread
From: Alan Cox @ 2007-12-04 16:48 UTC (permalink / raw)
To: Trolle Selander; +Cc: xen-devel
On Tue, 4 Dec 2007 17:32:39 +0100
"Trolle Selander" <trolle.selander@gmail.com> wrote:
> This patch adds 16550 emulation to qemu-dm. I still consider it a work in
I hope you mean 16550A, 16550 was a faulty part which lost bits and was
withdrawn. The 16550A is subtly different.
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] [QEMU-DM] Upgrade emulated UART to 16550A.
2007-12-04 16:48 ` Alan Cox
@ 2007-12-04 18:06 ` Trolle Selander
0 siblings, 0 replies; 6+ messages in thread
From: Trolle Selander @ 2007-12-04 18:06 UTC (permalink / raw)
To: Alan Cox; +Cc: xen-devel
[-- Attachment #1.1: Type: text/plain, Size: 628 bytes --]
Yes, I do mean 16550A-or-later. The code comments make this clear even if my
patch name and slightly rushed patched description didn't. The hardware
document I used was actually for a 16550D, but I believe there's no
difference on the programming/behavior level.
On Dec 4, 2007 5:48 PM, Alan Cox <alan@lxorguk.ukuu.org.uk> wrote:
> On Tue, 4 Dec 2007 17:32:39 +0100
> "Trolle Selander" <trolle.selander@gmail.com> wrote:
>
> > This patch adds 16550 emulation to qemu-dm. I still consider it a work
> in
>
> I hope you mean 16550A, 16550 was a faulty part which lost bits and was
> withdrawn. The 16550A is subtly different.
>
[-- Attachment #1.2: Type: text/html, Size: 974 bytes --]
[-- Attachment #2: Type: text/plain, Size: 138 bytes --]
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xensource.com
http://lists.xensource.com/xen-devel
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] [QEMU-DM] Upgrade emulated UART to 16550A.
2007-12-04 16:32 [PATCH] [QEMU-DM] Upgrade emulated UART to 16550A Trolle Selander
2007-12-04 16:48 ` Alan Cox
@ 2007-12-05 13:55 ` Keir Fraser
2007-12-05 14:24 ` Daniel P. Berrange
2 siblings, 0 replies; 6+ messages in thread
From: Keir Fraser @ 2007-12-05 13:55 UTC (permalink / raw)
To: Trolle Selander, xen-devel
[-- Attachment #1.1: Type: text/plain, Size: 1946 bytes --]
Please email me a signed-off-by line:
Signed-off-by: Trolle Selander <trolle.selander@gmail.com>
You can see the Developer¹s Certificate of Origin at:
http://old.linux-foundation.org/newsroom/press_releases/2004/2004_05_24_dco.
html
...which is what you are certifying by providing the signed-off-by
attribution for your patches.
-- Keir
On 4/12/07 16:32, "Trolle Selander" <trolle.selander@gmail.com> wrote:
> This patch adds 16550 emulation to qemu-dm. I still consider it a work in
> progress, but from my testing, it consistently performs better than the old
> code already, sometimes considerably so (on my laptop, dumping out data over
> serial from a HVM DomU -> pty in Dom0 was up to 5.3 times faster than with the
> old 16450 code). I can consistenly reach full 115200 baud speeds over physical
> serial lines when the virtual device is backed by a phys port, which I never
> could with the old code.
>
> There are still some things to be done. I want to add proper error handling,
> so that overflow/framing & parity errors on the physical port get detected and
> reported by the virtual port. Also, now that FIFOs are in place, I believe
> performance could be improved significantly by putting some code into the
> hypervisor so that reads & writes from the FIFOs don't have to exit into
> qemu-dm at all. I'm also reading up on the specs for newer uarts with deeper
> FIFOs.
>
> However, for now, I think this patch is already quite good, and I don't think
> I should sit on it any longer. I'm looking forward to hearing what results
> others will get with it.
>
> It applies on top of my previously posted patch for modem status/control line
> passthrough, so I'm re-posting that patch here as well to make things easier.
>
>
>
> _______________________________________________
> Xen-devel mailing list
> Xen-devel@lists.xensource.com
> http://lists.xensource.com/xen-devel
[-- Attachment #1.2: Type: text/html, Size: 2726 bytes --]
[-- Attachment #2: Type: text/plain, Size: 138 bytes --]
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xensource.com
http://lists.xensource.com/xen-devel
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] [QEMU-DM] Upgrade emulated UART to 16550A.
2007-12-04 16:32 [PATCH] [QEMU-DM] Upgrade emulated UART to 16550A Trolle Selander
2007-12-04 16:48 ` Alan Cox
2007-12-05 13:55 ` Keir Fraser
@ 2007-12-05 14:24 ` Daniel P. Berrange
2007-12-05 14:35 ` Trolle Selander
2 siblings, 1 reply; 6+ messages in thread
From: Daniel P. Berrange @ 2007-12-05 14:24 UTC (permalink / raw)
To: Trolle Selander; +Cc: xen-devel
On Tue, Dec 04, 2007 at 05:32:39PM +0100, Trolle Selander wrote:
> This patch adds 16550 emulation to qemu-dm. I still consider it a work in
> progress, but from my testing, it consistently performs better than the old
> code already, sometimes considerably so (on my laptop, dumping out data over
> serial from a HVM DomU -> pty in Dom0 was up to 5.3 times faster than with
> the old 16450 code). I can consistenly reach full 115200 baud speeds over
> physical serial lines when the virtual device is backed by a phys port,
> which I never could with the old code.
>
> There are still some things to be done. I want to add proper error handling,
> so that overflow/framing & parity errors on the physical port get detected
> and reported by the virtual port. Also, now that FIFOs are in place, I
> believe performance could be improved significantly by putting some code
> into the hypervisor so that reads & writes from the FIFOs don't have to exit
> into qemu-dm at all. I'm also reading up on the specs for newer uarts with
> deeper FIFOs.
>
> However, for now, I think this patch is already quite good, and I don't
> think I should sit on it any longer. I'm looking forward to hearing what
> results others will get with it.
>From a quick glance through the patches there doesn't appear to be anything
that is Xen specific in these patches. If I am correct in this understanding,
could you send the patches to upstream qemu-devel mailing lists, so Xen does
not have to carry this fork forever.
Regards,
Dan.
--
|=- Red Hat, Engineering, Emerging Technologies, Boston. +1 978 392 2496 -=|
|=- Perl modules: http://search.cpan.org/~danberr/ -=|
|=- Projects: http://freshmeat.net/~danielpb/ -=|
|=- GnuPG: 7D3B9505 F3C9 553F A1DA 4AC2 5648 23C1 B3DF F742 7D3B 9505 -=|
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] [QEMU-DM] Upgrade emulated UART to 16550A.
2007-12-05 14:24 ` Daniel P. Berrange
@ 2007-12-05 14:35 ` Trolle Selander
0 siblings, 0 replies; 6+ messages in thread
From: Trolle Selander @ 2007-12-05 14:35 UTC (permalink / raw)
To: Daniel P. Berrange; +Cc: xen-devel
[-- Attachment #1.1: Type: text/plain, Size: 2440 bytes --]
I don't think they'll apply cleanly to mainline qemu due to the
serial_get_token stuff, which is xen-specific, but it should be utterly
trivial to fix this. I'll make new patches against the latest mainline qemu
and submit them to qemu-devel as soon as I have time. I don't think qemu
will benefit as much from them performance-wise, but they definitely do
belong upstream.
On Dec 5, 2007 3:24 PM, Daniel P. Berrange <berrange@redhat.com> wrote:
> On Tue, Dec 04, 2007 at 05:32:39PM +0100, Trolle Selander wrote:
> > This patch adds 16550 emulation to qemu-dm. I still consider it a work
> in
> > progress, but from my testing, it consistently performs better than the
> old
> > code already, sometimes considerably so (on my laptop, dumping out data
> over
> > serial from a HVM DomU -> pty in Dom0 was up to 5.3 times faster than
> with
> > the old 16450 code). I can consistenly reach full 115200 baud speeds
> over
> > physical serial lines when the virtual device is backed by a phys port,
> > which I never could with the old code.
> >
> > There are still some things to be done. I want to add proper error
> handling,
> > so that overflow/framing & parity errors on the physical port get
> detected
> > and reported by the virtual port. Also, now that FIFOs are in place, I
> > believe performance could be improved significantly by putting some code
> > into the hypervisor so that reads & writes from the FIFOs don't have to
> exit
> > into qemu-dm at all. I'm also reading up on the specs for newer uarts
> with
> > deeper FIFOs.
> >
> > However, for now, I think this patch is already quite good, and I don't
> > think I should sit on it any longer. I'm looking forward to hearing what
> > results others will get with it.
>
> From a quick glance through the patches there doesn't appear to be
> anything
> that is Xen specific in these patches. If I am correct in this
> understanding,
> could you send the patches to upstream qemu-devel mailing lists, so Xen
> does
> not have to carry this fork forever.
>
> Regards,
> Dan.
> --
> |=- Red Hat, Engineering, Emerging Technologies, Boston. +1 978 392 2496
> -=|
> |=- Perl modules: http://search.cpan.org/~danberr/<http://search.cpan.org/%7Edanberr/> -=|
> |=- Projects: http://freshmeat.net/~danielpb/<http://freshmeat.net/%7Edanielpb/> -=|
> |=- GnuPG: 7D3B9505 F3C9 553F A1DA 4AC2 5648 23C1 B3DF F742 7D3B 9505
> -=|
>
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^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2007-12-05 14:35 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2007-12-04 16:32 [PATCH] [QEMU-DM] Upgrade emulated UART to 16550A Trolle Selander
2007-12-04 16:48 ` Alan Cox
2007-12-04 18:06 ` Trolle Selander
2007-12-05 13:55 ` Keir Fraser
2007-12-05 14:24 ` Daniel P. Berrange
2007-12-05 14:35 ` Trolle Selander
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