From: Andi Kleen <andi@firstfloor.org>
To: Keir Fraser <keir.fraser@eu.citrix.com>
Cc: Andi Kleen <andi@firstfloor.org>,
Trolle Selander <trolle.selander@gmail.com>,
xen-devel <xen-devel@lists.xensource.com>
Subject: Re: [PATCH] [RFC] More fp instructions for realmode emulation (Enables booting OS/2 as a HVM guest on Intel/VT hardware)
Date: Mon, 3 Mar 2008 19:11:50 +0100 [thread overview]
Message-ID: <20080303181149.GA13680@one.firstfloor.org> (raw)
In-Reply-To: <C3F1E625.1D616%keir.fraser@eu.citrix.com>
> We don't trust FXRSTOR but we do trust FXSAVE. The AMD manual says that
> FXRSTOR will #GP if 1s are written to MXCSR reserved bits, but I take this
> to be a cut-and-paste typo since FXSAVE does not write to MXCSR.
>
> If there's real evidence of FXSAVE causing #GP dependent on current FPU
> state, I'd be very happy to find out about it!
Sorry, double checked now the Intel docs. First I admit I don't
quite remember why it was originally done in Linux, but they
both use exception handlers.
The Intel docs say that #MF can happen for a pending FPU exception
in 64bit mode.
-Andi
next prev parent reply other threads:[~2008-03-03 18:11 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2008-02-29 22:14 [PATCH] [RFC] More fp instructions for realmode emulation (Enables booting OS/2 as a HVM guest on Intel/VT hardware) Trolle Selander
2008-03-01 8:46 ` Keir Fraser
2008-03-01 9:18 ` Keir Fraser
2008-03-03 12:18 ` Trolle Selander
2008-03-03 12:21 ` Keir Fraser
2008-03-03 14:52 ` Andi Kleen
2008-03-03 15:00 ` Keir Fraser
2008-03-03 16:59 ` Andi Kleen
2008-03-03 17:30 ` Keir Fraser
2008-03-03 18:11 ` Andi Kleen [this message]
2008-03-04 10:13 ` Keir Fraser
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