From: Paul Brook <paul@codesourcery.com>
To: qemu-devel@nongnu.org
Cc: Alex Williamson <alex.williamson@hp.com>,
kvm-devel <kvm@vger.kernel.org>
Subject: Re: [Qemu-devel] [PATCH] bios: Use the correct mask to size the PCI option ROM BAR
Date: Tue, 12 May 2009 23:41:40 +0100 [thread overview]
Message-ID: <200905122341.40706.paul@codesourcery.com> (raw)
In-Reply-To: <1242167590.4788.20.camel@2710p.home>
On Tuesday 12 May 2009, Alex Williamson wrote:
> Bit 0 is the enable bit, which we not only don't want to set, but
> it will stick and make us think it's an I/O port resource.
Why is the ROM slot special? Doesn't the same apply to all BARs?
Paul
WARNING: multiple messages have this Message-ID (diff)
From: Paul Brook <paul@codesourcery.com>
To: qemu-devel@nongnu.org
Cc: kvm-devel <kvm@vger.kernel.org>,
Alex Williamson <alex.williamson@hp.com>
Subject: Re: [Qemu-devel] [PATCH] bios: Use the correct mask to size the PCI option ROM BAR
Date: Tue, 12 May 2009 23:41:40 +0100 [thread overview]
Message-ID: <200905122341.40706.paul@codesourcery.com> (raw)
In-Reply-To: <1242167590.4788.20.camel@2710p.home>
On Tuesday 12 May 2009, Alex Williamson wrote:
> Bit 0 is the enable bit, which we not only don't want to set, but
> it will stick and make us think it's an I/O port resource.
Why is the ROM slot special? Doesn't the same apply to all BARs?
Paul
next prev parent reply other threads:[~2009-05-12 22:41 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2009-05-12 22:33 [PATCH] bios: Use the correct mask to size the PCI option ROM BAR Alex Williamson
2009-05-12 22:33 ` [Qemu-devel] " Alex Williamson
2009-05-12 22:41 ` Paul Brook [this message]
2009-05-12 22:41 ` Paul Brook
2009-05-12 23:47 ` Alex Williamson
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