[PATCH 0/3] Remove 'ehb' instructions from Cavium TLB handlers.

[PATCH 0/3] Remove 'ehb' instructions from Cavium TLB handlers.

[David Daney]

The Cavium Octeon CPU never needs the ehb instruction, this patch set
removes it resulting in shorter TLB handler hot paths.

I will reply with the three patches.

David Daney (3):
   MIPS: Allow R2 CPUs to turn off generation of 'ehb' instructions.
   MIPS: Remove execution hazard barriers for Octeon.
   MIPS: Remove dead case label.

  arch/mips/include/asm/cpu-features.h               |    4 ++++
  .../asm/mach-cavium-octeon/cpu-feature-overrides.h |    1 +
  arch/mips/mm/tlbex.c                               |    4 ++--
  3 files changed, 7 insertions(+), 2 deletions(-)

[PATCH 1/3] MIPS: Allow R2 CPUs to turn off generation of 'ehb' instructions.

[David Daney]

Some CPUs do not need ehb instructions after writing CP0 registers.
By allowing ehb generation to be overridden in
cpu-feature-overrides.h, we can save a few instructions in the TLB
handler hot paths.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
---
 arch/mips/include/asm/cpu-features.h |    4 ++++
 arch/mips/mm/tlbex.c                 |    3 ++-
 2 files changed, 6 insertions(+), 1 deletions(-)

diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index c0047f8..1cba4b2 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -147,6 +147,10 @@
 #define cpu_has_mips_r	(cpu_has_mips32r1 | cpu_has_mips32r2 | \
 			 cpu_has_mips64r1 | cpu_has_mips64r2)
 
+#ifndef cpu_has_mips_r2_exec_hazard
+#define cpu_has_mips_r2_exec_hazard cpu_has_mips_r2
+#endif
+
 /*
  * MIPS32, MIPS64, VR5500, IDT32332, IDT32334 and maybe a few other
  * pre-MIPS32/MIPS53 processors have CLO, CLZ.  For 64-bit kernels
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index 3548acf..4108674 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -258,7 +258,8 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l,
 	}
 
 	if (cpu_has_mips_r2) {
-		uasm_i_ehb(p);
+		if (cpu_has_mips_r2_exec_hazard)
+			uasm_i_ehb(p);
 		tlbw(p);
 		return;
 	}
-- 
1.6.0.6

[PATCH 2/3] MIPS: Remove execution hazard barriers for Octeon.

[David Daney]

The Octeon has no execution hazards, so we can remove them and save an
instruction per TLB handler invocation.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
---
 .../asm/mach-cavium-octeon/cpu-feature-overrides.h |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
index 04ce6e6..bb291f4 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
@@ -47,6 +47,7 @@
 #define cpu_has_mips32r2	0
 #define cpu_has_mips64r1	0
 #define cpu_has_mips64r2	1
+#define cpu_has_mips_r2_exec_hazard 0
 #define cpu_has_dsp		0
 #define cpu_has_mipsmt		0
 #define cpu_has_userlocal	0
-- 
1.6.0.6

Re: [PATCH 2/3] MIPS: Remove execution hazard barriers for Octeon.

[David VomLehn]

On Tue, May 12, 2009 at 12:41:54PM -0700, David Daney wrote:
> The Octeon has no execution hazards, so we can remove them and save an
> instruction per TLB handler invocation.
> 
> Signed-off-by: David Daney <ddaney@caviumnetworks.com>
> ---
>  .../asm/mach-cavium-octeon/cpu-feature-overrides.h |    1 +
>  1 files changed, 1 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
> index 04ce6e6..bb291f4 100644
> --- a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
> +++ b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
> @@ -47,6 +47,7 @@
>  #define cpu_has_mips32r2	0
>  #define cpu_has_mips64r1	0
>  #define cpu_has_mips64r2	1
> +#define cpu_has_mips_r2_exec_hazard 0
>  #define cpu_has_dsp		0
>  #define cpu_has_mipsmt		0
>  #define cpu_has_userlocal	0
> -- 
> 1.6.0.6

Simple enough that even I can understand it.

Reviewed by: David VomLehn <dvomlehn@cisco.com>

[PATCH 3/3] MIPS: Remove dead case label.

[David Daney]

CPU_CAVIUM_OCTEON is mips_r2 which is handled before the switch.  This
label in the switch statement is dead code, so we remove it.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
---
 arch/mips/mm/tlbex.c |    1 -
 1 files changed, 0 insertions(+), 1 deletions(-)

diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index 4108674..4dc4f3e 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -311,7 +311,6 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l,
 	case CPU_BCM3302:
 	case CPU_BCM4710:
 	case CPU_LOONGSON2:
-	case CPU_CAVIUM_OCTEON:
 	case CPU_R5500:
 		if (m4kc_tlbp_war())
 			uasm_i_nop(p);
-- 
1.6.0.6

Re: [PATCH 3/3] MIPS: Remove dead case label.

[David VomLehn]

On Tue, May 12, 2009 at 12:41:55PM -0700, David Daney wrote:
> CPU_CAVIUM_OCTEON is mips_r2 which is handled before the switch.  This
> label in the switch statement is dead code, so we remove it.
> 
> Signed-off-by: David Daney <ddaney@caviumnetworks.com>
> ---
>  arch/mips/mm/tlbex.c |    1 -
>  1 files changed, 0 insertions(+), 1 deletions(-)
> 
> diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
> index 4108674..4dc4f3e 100644
> --- a/arch/mips/mm/tlbex.c
> +++ b/arch/mips/mm/tlbex.c
> @@ -311,7 +311,6 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l,
>  	case CPU_BCM3302:
>  	case CPU_BCM4710:
>  	case CPU_LOONGSON2:
> -	case CPU_CAVIUM_OCTEON:
>  	case CPU_R5500:
>  		if (m4kc_tlbp_war())
>  			uasm_i_nop(p);

Fewer lines of code is good...

Reviewed by: David VomLehn <dvomlehn@cisco.com>

Re: [PATCH 0/3] Remove 'ehb' instructions from Cavium TLB handlers.

[Ralf Baechle]

On Tue, May 12, 2009 at 12:40:33PM -0700, David Daney wrote:

> The Cavium Octeon CPU never needs the ehb instruction, this patch set
> removes it resulting in shorter TLB handler hot paths.

Whole series applied for -queue and -next.

Thanks,

  Ralf