WM8731 using I2S on omap3 McBSP2 issues

WM8731 using I2S on omap3 McBSP2 issues

[Rick Bronson]

Hi,

  I'm working on getting a WM8731 (in SLAVE) working using I2S on
omap3 McBSP2 (in MASTER).

Here is the hardware:

http://www.efn.org/~rick/pub/wm8731.jpg

  Here are the PADCONF's and the pins they hook to on the WM8731:

 /*Audio Interface for csb740 */\
 MUX_VAL(CP(McBSP2_FSX),  (OFF_OUT_PD | IDIS | PTU | EN | M0)) /* McBSP2_FSX -> I2S_FRM -> LRCLK -> DACLRC and ADCLRC*/\
 MUX_VAL(CP(McBSP2_CLKX), (OFF_OUT_PD | IDIS | PTU | EN | M0)) /* McBSP2_CLKX -> I2S_CLK -> I2S_BCLK -> BCLK */\
 MUX_VAL(CP(McBSP2_DR),   (OFF_IN_PD  | IEN  | PTD | DIS | M0)) /* McBSP2_DR <- I2S_RXD <- ACDDAT */\
 MUX_VAL(CP(McBSP2_DX),   (OFF_OUT_PD | IDIS | PTU | EN | M0)) /* McBSP2_DX -> I2S_TXD -> DACDAT */\
 MUX_VAL(CP(McBSP_CLKS),  (OFF_IN_PD  | IEN  | PTD | DIS | M0)) /* McBSP_CLKS <- I2S_MCLK <- CLKOUT */\

 My kernel is "2.6.29-rc3-omap1", here's what I see at bootup:

1 WM8731 Audio Codec 0.13<6>asoc: WM8731 <-> omap-mcbsp-dai-0 mapping ok
2 ALSA device list:
3  #0: omap3csb740 (WM8731)
...
4 beagle:~# aplay test48000.wav
5 Playing WAVE 'test48000.wav' : Signed 16 bit Little Endian, Rate 48000 Hz, Stereo
6 aplay: pcm_write:1269: write error: Input/output error

  I get no audio output, other than a "click" when the 8731 is
initialized upon boot.  When I look at the signals the McBSP2_DX line
just goes low for the duration of the "aplay", it does not toggle. The
other lines look fine.  The file is at
http://www.efn.org/~rick/pub/omap3csb740.c but roughly, here's what
I'm doing:

static struct snd_soc_dai_link omap3csb740_dai = {
...
 .cpu_dai = &omap_mcbsp_dai[0], /* use 1st one */

static int __init omap3csb740_soc_init(void)
...
 *(unsigned int *)omap_mcbsp_dai[0].private_data = 1; /* McBSP2 */
 *(unsigned int *)omap3csb740_dai.cpu_dai->private_data = 1; /* McBSP2 debug only? */

static int omap3csb740_hw_params(struct snd_pcm_substream *substream,
...
 ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S |
  SND_SOC_DAIFMT_NB_NF |  SND_SOC_DAIFMT_CBS_CFS);
 ret = snd_soc_dai_set_fmt(cpu_dai,  SND_SOC_DAIFMT_I2S |
  SND_SOC_DAIFMT_NB_NF |  SND_SOC_DAIFMT_CBS_CFS);
 ret = snd_soc_dai_set_sysclk(codec_dai, 0, 12288000,   SND_SOC_CLOCK_IN);
 ret = snd_soc_dai_set_sysclk(cpu_dai, OMAP_MCBSP_SYSCLK_CLKS_EXT, 0,
   SND_SOC_CLOCK_IN);
 ret = snd_soc_dai_set_clkdiv(cpu_dai, OMAP_MCBSP_CLKGDV, 256);

  Any help is greatly appreciated.

  Rick Bronson

Re: WM8731 using I2S on omap3 McBSP2 issues

[Mark Brown]

On Thu, Sep 24, 2009 at 10:06:07AM -0700, Rick Bronson wrote:

>  MUX_VAL(CP(McBSP_CLKS),  (OFF_IN_PD  | IEN  | PTD | DIS | M0)) /* McBSP_CLKS <- I2S_MCLK <- CLKOUT */\

...

> 5 Playing WAVE 'test48000.wav' : Signed 16 bit Little Endian, Rate 48000 Hz, Stereo
> 6 aplay: pcm_write:1269: write error: Input/output error

This suggests that the DMA isn't happening which usually means that the
CPU isn't seeing all the clocks it's supposed to.  I'm not familiar
enough with the OMAP internals to know if you've set the CPU up
properly.

>   I get no audio output, other than a "click" when the 8731 is
> initialized upon boot.  When I look at the signals the McBSP2_DX line
> just goes low for the duration of the "aplay", it does not toggle. The
> other lines look fine.  The file is at

If you try a record then does the ADCDAT line show a signal?

Re: WM8731 using I2S on omap3 McBSP2 issues

[Rick Bronson]

Mark,

> This suggests that the DMA isn't happening which usually means that the
> CPU isn't seeing all the clocks it's supposed to.  I'm not familiar
> enough with the OMAP internals to know if you've set the CPU up
> properly.

  I've poured over the relavent code for this and am pretty sure I
don't need to touch it.  The same code works on the beagleboard, at
least the DMA part.  But you never know...

> >   I get no audio output, other than a "click" when the 8731 is
> > initialized upon boot.  When I look at the signals the McBSP2_DX line
> > just goes low for the duration of the "aplay", it does not toggle. The
> > other lines look fine.  The file is at
> 
> If you try a record then does the ADCDAT line show a signal?

  I tried this and the ADCDAT does show a signal.  See
http://www.efn.org/~rick/pub/win10586.jpg  The bottom five traces are
as follows:

McBSP2_CLKX -> I2S_CLK -> I2S_BCLK -> BCLK */\
McBSP2_FSX -> I2S_FRM -> LRCLK -> DACLRC and ADCLRC*/\
McBSP2_DR <- I2S_RXD <- ACDDAT */\
McBSP_CLKS <- I2S_MCLK <- CLKOUT */\
McBSP2_DX -> I2S_TXD -> DACDAT */\

  BTW, when I do a aplay, the trace looks the same except ACDDAT is
low.

  I still get a write error though:

beagle:~# arecord -t wav -f cd -d 1500 dar.wav                                  
Recording WAVE 'dar.wav' : Signed 16 bit Little Endian, Rate 44100 Hz, Stereo   
arecord: pcm_read:1348: read error: Input/output error                          

  Rick

Re: WM8731 using I2S on omap3 McBSP2 issues

[Mark Brown]

On Thu, Sep 24, 2009 at 11:00:52AM -0700, Rick Bronson wrote:
> Mark,

> > This suggests that the DMA isn't happening which usually means that the
> > CPU isn't seeing all the clocks it's supposed to.  I'm not familiar
> > enough with the OMAP internals to know if you've set the CPU up
> > properly.

>   I've poured over the relavent code for this and am pretty sure I
> don't need to touch it.  The same code works on the beagleboard, at
> least the DMA part.  But you never know...

You shouldn't need to touch the DMA code itself, it's normally an issue
with the clocks and/or the pinmux code not managing to get the signals
required to clock the data transfer.

>   BTW, when I do a aplay, the trace looks the same except ACDDAT is
> low.

Yes, that's what I'd expect - this was just an attempt to confirm that
the CODEC is happy.

Re: WM8731 using I2S on omap3 McBSP2 issues

[Rick Bronson]

> You shouldn't need to touch the DMA code itself, it's normally an issue
> with the clocks and/or the pinmux code not managing to get the signals
> required to clock the data transfer.

  I noticed the dma code has been changed from what I have.

  Also noticed that the beagleboard is getting DMA interrupts when I
"aplay":

cat /proc/interrupts | grep DMA

 12:       4646        INTC  DMA   

  but I'm not.  As I mentioned, I'm at "2.6.29-rc3-omap1", anyone
think there is a problem with pcm DMA's in that version?

  Thanks

  Rick

Re: WM8731 using I2S on omap3 McBSP2 issues

[Mark Brown]

On Thu, Sep 24, 2009 at 03:37:28PM -0700, Rick Bronson wrote:

>   Also noticed that the beagleboard is getting DMA interrupts when I
> "aplay":

> cat /proc/interrupts | grep DMA

>  12:       4646        INTC  DMA   

That's just the same symptom - the I/O error that aplay reports is a
lack of interrupts reporting that audio is moving through the system.

>   but I'm not.  As I mentioned, I'm at "2.6.29-rc3-omap1", anyone
> think there is a problem with pcm DMA's in that version?

Re: WM8731 using I2S on omap3 McBSP2 issues

[Peter Ujfalusi]

Hello,

On Thursday 24 September 2009 20:06:07 ext Rick Bronson wrote:
> Hi,
> 
>   I'm working on getting a WM8731 (in SLAVE) working using I2S on
> omap3 McBSP2 (in MASTER).

 
> static int omap3csb740_hw_params(struct snd_pcm_substream *substream,
> ...
>  ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S |
>   SND_SOC_DAIFMT_NB_NF |  SND_SOC_DAIFMT_CBS_CFS);
>  ret = snd_soc_dai_set_fmt(cpu_dai,  SND_SOC_DAIFMT_I2S |
>   SND_SOC_DAIFMT_NB_NF |  SND_SOC_DAIFMT_CBS_CFS);
>  ret = snd_soc_dai_set_sysclk(codec_dai, 0, 12288000,   SND_SOC_CLOCK_IN);
>  ret = snd_soc_dai_set_sysclk(cpu_dai, OMAP_MCBSP_SYSCLK_CLKS_EXT, 0,
>    SND_SOC_CLOCK_IN);

I think the problem is here.
The MCBSP_CLKS pin is connected to CLK256FS pin of TWL4030 (or TPA).
Since you are not using the TWL codec, there will be no clock on the MCBSP_CLKS 
pin, thus no functional clock for McBSP, thus no bits are shifted in or out.
You can try to use the internal functional clock:

  ret = snd_soc_dai_set_sysclk(cpu_dai, OMAP_MCBSP_SYSCLK_CLKS_FCLK, 0,
    SND_SOC_CLOCK_IN);

Than set the correct divider, which depends on the frequency you would like to 
play. The source for the CLKS_FCLK is (in case of McBSP2) PER_96M_FCLK, so 
96MHz. Now you have to divide this to get the correct value, as I recall quite a 
long time ago there were some discussion about this here, and I have sent some 
'formula' to calculate it, but I can not find it now :(

>  ret = snd_soc_dai_set_clkdiv(cpu_dai, OMAP_MCBSP_CLKGDV, 256);
> 
>   Any help is greatly appreciated.
> 
>   Rick Bronson
> 

-- 
Péter

Re: WM8731 using I2S on omap3 McBSP2 issues

[Peter Ujfalusi]

On Friday 25 September 2009 09:03:06 Ujfalusi Peter (Nokia-D/Tampere) wrote:
> Hello,
> 
> On Thursday 24 September 2009 20:06:07 ext Rick Bronson wrote:
> > Hi,
> >
> >   I'm working on getting a WM8731 (in SLAVE) working using I2S on
> > omap3 McBSP2 (in MASTER).
> >
> >
> > static int omap3csb740_hw_params(struct snd_pcm_substream *substream,
> > ...
> >  ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S |
> >   SND_SOC_DAIFMT_NB_NF |  SND_SOC_DAIFMT_CBS_CFS);
> >  ret = snd_soc_dai_set_fmt(cpu_dai,  SND_SOC_DAIFMT_I2S |
> >   SND_SOC_DAIFMT_NB_NF |  SND_SOC_DAIFMT_CBS_CFS);
> >  ret = snd_soc_dai_set_sysclk(codec_dai, 0, 12288000,  
> > SND_SOC_CLOCK_IN); ret = snd_soc_dai_set_sysclk(cpu_dai,
> > OMAP_MCBSP_SYSCLK_CLKS_EXT, 0, SND_SOC_CLOCK_IN);
> 
> I think the problem is here.
> The MCBSP_CLKS pin is connected to CLK256FS pin of TWL4030 (or TPA).

This applies for the Beagle board, which I thought that you are using that from 
this line:
> 4 beagle:~# aplay test48000.wav

Can you check that the clock is running between
CLKOUT (WM8731) -> McBSP_CLKS (OMAP3) pins?

If the clock is missing, than the functional clock is not running.

> Since you are not using the TWL codec, there will be no clock on the
>  MCBSP_CLKS pin, thus no functional clock for McBSP, thus no bits are
>  shifted in or out. You can try to use the internal functional clock:
> 
>   ret = snd_soc_dai_set_sysclk(cpu_dai, OMAP_MCBSP_SYSCLK_CLKS_FCLK, 0,
>     SND_SOC_CLOCK_IN);
> 
> Than set the correct divider, which depends on the frequency you would like
>  to play. The source for the CLKS_FCLK is (in case of McBSP2) PER_96M_FCLK,
>  so 96MHz. Now you have to divide this to get the correct value, as I
>  recall quite a long time ago there were some discussion about this here,
>  and I have sent some 'formula' to calculate it, but I can not find it now
>  :(
> 
> >  ret = snd_soc_dai_set_clkdiv(cpu_dai, OMAP_MCBSP_CLKGDV, 256);
> >
> >   Any help is greatly appreciated.
> >
> >   Rick Bronson
> 

-- 
Péter

Re: WM8731 using I2S on omap3 McBSP2 issues

[Rick Bronson]

Hi Peter,

  Thanks very much for the help.

> I think the problem is here.
> The MCBSP_CLKS pin is connected to CLK256FS pin of TWL4030 (or TPA).
> Since you are not using the TWL codec, there will be no clock on the MCBSP_CLKS
> pin, thus no functional clock for McBSP, thus no bits are shifted in or out.
> You can try to use the internal functional clock:
> 
>   ret = snd_soc_dai_set_sysclk(cpu_dai, OMAP_MCBSP_SYSCLK_CLKS_FCLK, 0,
>     SND_SOC_CLOCK_IN);

  I have checked the CLKOUT (WM8731) -> McBSP_CLKS (OMAP3) pin and it
has a 12288000 clock on it.  I've tried using the internal clock as
you show above, just to see if I get anything out on DX but I get the
same thing: DX just goes low for the "aplay" duration.

  Any idea why I'm not getting DMA interrupts?  This would indeed
cause no data at DX.  omap2_dma_irq_handler() never gets called but
omap_init_dma() and omap_start_dma() get called.  Do you think there
may be any issues with my DMA code (specifically
arch/arm/plat-omap/dma.c).  As I mentioned, I'm at "2.6.29-rc3-omap1"

  Thanks,

  Rick

Re: WM8731 using I2S on omap3 McBSP2 issues

[Rick Bronson]

Hi Peter,

  I forgot to tell you that if I deliberately misconfigure the
McBXP_CLKS pin so that it's an output, the FSX -> DACLRC/ADCLRC signal
stops.  This should indicate that the CLKOUT signal is actually making
it to the CLKS pin on the OMAP.  Right?

  Rick

Re: WM8731 using I2S on omap3 McBSP2 issues

[Jarkko Nikula]

On Fri, 25 Sep 2009 07:31:47 -0700
Rick Bronson <rick@efn.org> wrote:

> Hi Peter,
> 
>   I forgot to tell you that if I deliberately misconfigure the
> McBXP_CLKS pin so that it's an output, the FSX -> DACLRC/ADCLRC signal
> stops.  This should indicate that the CLKOUT signal is actually making
> it to the CLKS pin on the OMAP.  Right?
> 
Yes it is indicating so. I read through this thread I didn't find any
simple reason why it's not working. Your setup is similar with the
Pandora, i.e. McBSP functional clock is coming the codec and codec is
slave.

The McBSP is operating if the FSX and CLKX are toggling in this setup.
Is it so that you don't get any DMA interrupts or just few of them?
Your CLKGDV divisor value 256 means too low bit clock and sample rate
for both external 12.288 MHz and internal 96 MHz but still the DMA
should be running (if there is no bug with this divisor value).

Can you try divisor value 8 does it work then? For 48 kHz sample rate
with I2S you need a bit clock of 48 kHz*2*16 = 1.536 MHz and this you
get by dividing the 12.288 MHz with 8.


-- 
Jarkko

Re: WM8731 using I2S on omap3 McBSP2 issues

[Rick Bronson]

Hi Peter,

> Yes it is indicating so. I read through this thread I didn't find any
> simple reason why it's not working. Your setup is similar with the
> Pandora, i.e. McBSP functional clock is coming the codec and codec is
> slave.

  Yes, I pretty much used the pandora as an example to write mine.

> The McBSP is operating if the FSX and CLKX are toggling in this setup.
> Is it so that you don't get any DMA interrupts or just few of them?

  I don't get any DMA int's:

~# cat /proc/interrupts                                                  
           CPU0                                                                 
 11:          0        INTC  prcm                                               
 12:          0        INTC  DMA                                                
 25:          0        INTC  dispc                                              
 37:       5003        INTC  gp timer                                           
 56:       3425        INTC  i2c_omap                                           
 62:          0        INTC  McBSP                                              
 63:          0        INTC  McBSP                                              


> Your CLKGDV divisor value 256 means too low bit clock and sample rate
> for both external 12.288 MHz and internal 96 MHz but still the DMA
> should be running (if there is no bug with this divisor value).
> Can you try divisor value 8 does it work then? For 48 kHz sample rate
> with I2S you need a bit clock of 48 kHz*2*16 = 1.536 MHz and this you
> get by dividing the 12.288 MHz with 8.
> 

  Yes, I had tried 8 before and just tried it now.  Same result.  It
really seems like there is a DMA issue.  Can you think of anything
else to try before I dive into the DMA code?

  Rick

Re: WM8731 using I2S on omap3 McBSP2 issues

[Jarkko Nikula]

On Sat, 26 Sep 2009 08:59:52 -0700
Rick Bronson <rick@efn.org> wrote:

>   Yes, I had tried 8 before and just tried it now.  Same result.  It
> really seems like there is a DMA issue.  Can you think of anything
> else to try before I dive into the DMA code?
> 
Ok, that wasn't the reason.

Have you tried to reverse roles of codec and omap? I.e. by using
the codec as a master and omap as a slave with SND_SOC_DAIFMT_CBM_CFM.

I don't think there is any HW reason as you have seen the bit-clock and
frame sync signals toggling but I remember one case few years back
where codec had slight too high capacitive load on the bit-clock line.
That was then causing unstable frame sync as it was internally derived
directly from the bit-clock pin without any buffer. Bit-clock signal
looked just fine on oscilloscope but wasn't well enough for internal
circuits of the cpu.

So if assuming similar problem here, I could imagine that if the FSX is
used similar way directly inside the omap and if signal is not well
enough, the McBSP and DMA may not be running.

This migh be a bit far reason to look for but at least easy to try by
switching the roles as then the codec is driving the both bit-clock and
fs.


-- 
Jarkko

Re: WM8731 using I2S on omap3 McBSP2 issues

[Rick Bronson]

Hi Peter,

  Thanks for the help.

  I don't believe it's possible for me to try the master/slave switch.
Please take a look at http://www.efn.org/~rick/pub/wm8731.jpg Note
that DACLRC and ADCLRC are connected.  This requires me to run as
slave, right?  Our bit clock line is buffered so I don't think that
will be a problem.

  Rick

> >   Yes, I had tried 8 before and just tried it now.  Same result.  It
> > really seems like there is a DMA issue.  Can you think of anything
> > else to try before I dive into the DMA code?
> >
> Ok, that wasn't the reason.
> 
> Have you tried to reverse roles of codec and omap? I.e. by using
> the codec as a master and omap as a slave with SND_SOC_DAIFMT_CBM_CFM.
> 
> I don't think there is any HW reason as you have seen the bit-clock and
> frame sync signals toggling but I remember one case few years back
> where codec had slight too high capacitive load on the bit-clock line.
> That was then causing unstable frame sync as it was internally derived
> directly from the bit-clock pin without any buffer. Bit-clock signal
> looked just fine on oscilloscope but wasn't well enough for internal
> circuits of the cpu.
> 
> So if assuming similar problem here, I could imagine that if the FSX is
> used similar way directly inside the omap and if signal is not well
> enough, the McBSP and DMA may not be running.
> 
> This migh be a bit far reason to look for but at least easy to try by
> switching the roles as then the codec is driving the both bit-clock and
> fs.
> 
> 

Re: WM8731 using I2S on omap3 McBSP2 issues

[Mark Brown]

On Mon, Sep 28, 2009 at 09:07:26AM -0700, Rick Bronson wrote:

>   I don't believe it's possible for me to try the master/slave switch.
> Please take a look at http://www.efn.org/~rick/pub/wm8731.jpg Note
> that DACLRC and ADCLRC are connected.  This requires me to run as
> slave, right?  Our bit clock line is buffered so I don't think that
> will be a problem.

Tying the DAC and ADC LRCLKs together should be fine in either master or
slave mode, I'd expect (but I am not a hardware engineer).

Re: WM8731 using I2S on omap3 McBSP2 issues

[Rick Bronson]

Peter,

  I'm getting a XUNDFLSTAT (indicates a real underflow condition) and
XEMPTYEOF (Transmit buffer empty at end of frame) in
MCBSPLP_IRQSTATUS_REG.  Does this tell you anything?

  Rick

Re: WM8731 using I2S on omap3 McBSP2 issues

[Peter Ujfalusi]

On Tuesday 29 September 2009 00:15:10 ext Rick Bronson wrote:
> Peter,
> 
>   I'm getting a XUNDFLSTAT (indicates a real underflow condition) and
> XEMPTYEOF (Transmit buffer empty at end of frame) in
> MCBSPLP_IRQSTATUS_REG.  Does this tell you anything?

Hmm, this actually means that the DMA is not filling the McBSP buffer.
Since there is no data written in the McBSP buffer, it is shifting out 0 which 
is what you have observed on the DX line (goes low for the duration of aplay).

I have used McBSP as master on 2.6.28 kernel and I can not recall any big 
changes regarding to OMAP McBSP/DMA in between 28 and 29, so I'm a bit puzzled 
on this...

> 
>   Rick
> 

-- 
Péter