[PATCH] MIPS: Alchemy: sleepcode without compile-time cputype dependencies

[PATCH] MIPS: Alchemy: sleepcode without compile-time cputype dependencies

[Manuel Lauss]

Split the low-level sleepcode into per-memory-controller-generation
functions and figure out which one to call at runtime instead of
relying on compile-time-defined cpu types.

Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com>
---
Works on the DB1200.

 arch/mips/alchemy/common/power.c           |   12 +++-
 arch/mips/alchemy/common/sleeper.S         |   81 ++++++++++++++++++----------
 arch/mips/include/asm/mach-au1x00/au1000.h |    3 +-
 3 files changed, 64 insertions(+), 32 deletions(-)

diff --git a/arch/mips/alchemy/common/power.c b/arch/mips/alchemy/common/power.c
index 6ab7b42..c07101c 100644
--- a/arch/mips/alchemy/common/power.c
+++ b/arch/mips/alchemy/common/power.c
@@ -209,9 +209,15 @@ static void restore_core_regs(void)
 
 void au_sleep(void)
 {
-	save_core_regs();
-	au1xxx_save_and_sleep();
-	restore_core_regs();
+	int cpuid = alchemy_get_cputype();
+	if (cpuid != ALCHEMY_CPU_UNKNOWN) {
+		save_core_regs();
+		if (cpuid <= ALCHEMY_CPU_AU1500)
+			alchemy_sleep_au1000();
+		else if (cpuid <= ALCHEMY_CPU_AU1200)
+			alchemy_sleep_au1550();
+		restore_core_regs();
+	}
 }
 
 #endif	/* CONFIG_PM */
diff --git a/arch/mips/alchemy/common/sleeper.S b/arch/mips/alchemy/common/sleeper.S
index 4f4b167..77f3c74 100644
--- a/arch/mips/alchemy/common/sleeper.S
+++ b/arch/mips/alchemy/common/sleeper.S
@@ -22,10 +22,9 @@
 	.set noat
 	.align	5
 
-/* Save all of the processor general registers and go to sleep.
- * A wakeup condition will get us back here to restore the registers.
- */
-LEAF(au1xxx_save_and_sleep)
+
+/* preparatory stuff */
+.macro	SETUP_SLEEP
 	subu	sp, PT_SIZE
 	sw	$1, PT_R1(sp)
 	sw	$2, PT_R2(sp)
@@ -69,12 +68,32 @@ LEAF(au1xxx_save_and_sleep)
 	 */
 	lui	t3, 0xb190		/* sys_xxx */
 	sw	sp, 0x0018(t3)
-	la	k0, 3f			/* resume path */
+	la	k0, alchemy_sleep_wakeup	/* resume path */
 	sw	k0, 0x001c(t3)
+.endm
 
-	/* Put SDRAM into self refresh:  Preload instructions into cache,
-	 * issue a precharge, auto/self refresh, then sleep commands to it.
-	 */
+.macro	DO_SLEEP
+	/* put power supply and processor to sleep */
+	sw	zero, 0x0078(t3)	/* sys_slppwr */
+	sync
+	sw	zero, 0x007c(t3)	/* sys_sleep */
+	sync
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+.endm
+
+/* sleep code for Au1000/Au1100/Au1500 memory controller type */
+LEAF(alchemy_sleep_au1000)
+
+	SETUP_SLEEP
+
+	/* cache following instructions, as memory gets put to sleep */
 	la	t0, 1f
 	.set	mips3
 	cache	0x14, 0(t0)
@@ -84,17 +103,32 @@ LEAF(au1xxx_save_and_sleep)
 	.set	mips0
 
 1:	lui 	a0, 0xb400		/* mem_xxx */
-#if defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1100) ||	\
-    defined(CONFIG_SOC_AU1500)
 	sw	zero, 0x001c(a0) 	/* Precharge */
 	sync
 	sw	zero, 0x0020(a0)	/* Auto Refresh */
 	sync
 	sw	zero, 0x0030(a0)  	/* Sleep */
 	sync
-#endif
 
-#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
+	DO_SLEEP
+
+END(alchemy_sleep_au1000)
+
+/* sleep code for Au1550/Au1200 memory controller type */
+LEAF(alchemy_sleep_au1550)
+
+	SETUP_SLEEP
+
+	/* cache following instructions, as memory gets put to sleep */
+	la	t0, 1f
+	.set	mips3
+	cache	0x14, 0(t0)
+	cache	0x14, 32(t0)
+	cache	0x14, 64(t0)
+	cache	0x14, 96(t0)
+	.set	mips0
+
+1:	lui 	a0, 0xb400		/* mem_xxx */
 	sw	zero, 0x08c0(a0) 	/* Precharge */
 	sync
 	sw	zero, 0x08d0(a0)	/* Self Refresh */
@@ -114,26 +148,17 @@ LEAF(au1xxx_save_and_sleep)
 	and 	t1, t0, t1		/* clear CE[1:0] */
 	sw 	t1, 0x0840(a0)		/* mem_sdconfiga */
 	sync
-#endif
 
-	/* put power supply and processor to sleep */
-	sw	zero, 0x0078(t3)	/* sys_slppwr */
-	sync
-	sw	zero, 0x007c(t3)	/* sys_sleep */
-	sync
-	nop
-	nop
-	nop
-	nop
-	nop
-	nop
-	nop
-	nop
+	DO_SLEEP
+
+END(alchemy_sleep_au1550)
+
 
 	/* This is where we return upon wakeup.
 	 * Reload all of the registers and return.
 	 */
-3:	lw	k0, 0x20(sp)
+LEAF(alchemy_sleep_wakeup)
+	lw	k0, 0x20(sp)
 	mtc0	k0, CP0_STATUS
 	lw	k0, 0x1c(sp)
 	mtc0	k0, CP0_CONTEXT
@@ -169,4 +194,4 @@ LEAF(au1xxx_save_and_sleep)
 	lw	$31, PT_R31(sp)
 	jr	ra
 	 addiu	sp, PT_SIZE
-END(au1xxx_save_and_sleep)
+END(alchemy_sleep_wakeup)
diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h
index ae07423..cb91714 100644
--- a/arch/mips/include/asm/mach-au1x00/au1000.h
+++ b/arch/mips/include/asm/mach-au1x00/au1000.h
@@ -188,7 +188,8 @@ extern unsigned long get_au1x00_uart_baud_base(void);
 extern unsigned long au1xxx_calc_clock(void);
 
 /* PM: arch/mips/alchemy/common/sleeper.S, power.c, irq.c */
-void au1xxx_save_and_sleep(void);
+void alchemy_sleep_au1000(void);
+void alchemy_sleep_au1550(void);
 void au_sleep(void);
 void save_au1xxx_intctl(void);
 void restore_au1xxx_intctl(void);
-- 
1.7.0.2

[RFC PATCH] MIPS: Alchemy: add sysdev for both irq controllers

[Manuel Lauss]

From: Manuel Lauss <mano@roarinelk.homelinux.net>

Use a sysdev to implement PM methods for the Au1000 interrupt controllers.

Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com>
---
Works on DB1200, not sure though whether this is the correct approach. 
Applies cleanly only on top of "sleepcode-without-compile-time-cputype"
patch.

 arch/mips/alchemy/common/irq.c             |  196 ++++++++++++++++------------
 arch/mips/alchemy/common/power.c           |    5 -
 arch/mips/include/asm/mach-au1x00/au1000.h |    2 -
 3 files changed, 112 insertions(+), 91 deletions(-)

diff --git a/arch/mips/alchemy/common/irq.c b/arch/mips/alchemy/common/irq.c
index b2821ac..fd0e577 100644
--- a/arch/mips/alchemy/common/irq.c
+++ b/arch/mips/alchemy/common/irq.c
@@ -29,6 +29,7 @@
 #include <linux/init.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
+#include <linux/sysdev.h>
 
 #include <asm/irq_cpu.h>
 #include <asm/mipsregs.h>
@@ -216,90 +217,6 @@ struct au1xxx_irqmap au1200_irqmap[] __initdata = {
 };
 
 
-#ifdef CONFIG_PM
-
-/*
- * Save/restore the interrupt controller state.
- * Called from the save/restore core registers as part of the
- * au_sleep function in power.c.....maybe I should just pm_register()
- * them instead?
- */
-static unsigned int	sleep_intctl_config0[2];
-static unsigned int	sleep_intctl_config1[2];
-static unsigned int	sleep_intctl_config2[2];
-static unsigned int	sleep_intctl_src[2];
-static unsigned int	sleep_intctl_assign[2];
-static unsigned int	sleep_intctl_wake[2];
-static unsigned int	sleep_intctl_mask[2];
-
-void save_au1xxx_intctl(void)
-{
-	sleep_intctl_config0[0] = au_readl(IC0_CFG0RD);
-	sleep_intctl_config1[0] = au_readl(IC0_CFG1RD);
-	sleep_intctl_config2[0] = au_readl(IC0_CFG2RD);
-	sleep_intctl_src[0] = au_readl(IC0_SRCRD);
-	sleep_intctl_assign[0] = au_readl(IC0_ASSIGNRD);
-	sleep_intctl_wake[0] = au_readl(IC0_WAKERD);
-	sleep_intctl_mask[0] = au_readl(IC0_MASKRD);
-
-	sleep_intctl_config0[1] = au_readl(IC1_CFG0RD);
-	sleep_intctl_config1[1] = au_readl(IC1_CFG1RD);
-	sleep_intctl_config2[1] = au_readl(IC1_CFG2RD);
-	sleep_intctl_src[1] = au_readl(IC1_SRCRD);
-	sleep_intctl_assign[1] = au_readl(IC1_ASSIGNRD);
-	sleep_intctl_wake[1] = au_readl(IC1_WAKERD);
-	sleep_intctl_mask[1] = au_readl(IC1_MASKRD);
-}
-
-/*
- * For most restore operations, we clear the entire register and
- * then set the bits we found during the save.
- */
-void restore_au1xxx_intctl(void)
-{
-	au_writel(0xffffffff, IC0_MASKCLR); au_sync();
-
-	au_writel(0xffffffff, IC0_CFG0CLR); au_sync();
-	au_writel(sleep_intctl_config0[0], IC0_CFG0SET); au_sync();
-	au_writel(0xffffffff, IC0_CFG1CLR); au_sync();
-	au_writel(sleep_intctl_config1[0], IC0_CFG1SET); au_sync();
-	au_writel(0xffffffff, IC0_CFG2CLR); au_sync();
-	au_writel(sleep_intctl_config2[0], IC0_CFG2SET); au_sync();
-	au_writel(0xffffffff, IC0_SRCCLR); au_sync();
-	au_writel(sleep_intctl_src[0], IC0_SRCSET); au_sync();
-	au_writel(0xffffffff, IC0_ASSIGNCLR); au_sync();
-	au_writel(sleep_intctl_assign[0], IC0_ASSIGNSET); au_sync();
-	au_writel(0xffffffff, IC0_WAKECLR); au_sync();
-	au_writel(sleep_intctl_wake[0], IC0_WAKESET); au_sync();
-	au_writel(0xffffffff, IC0_RISINGCLR); au_sync();
-	au_writel(0xffffffff, IC0_FALLINGCLR); au_sync();
-	au_writel(0x00000000, IC0_TESTBIT); au_sync();
-
-	au_writel(0xffffffff, IC1_MASKCLR); au_sync();
-
-	au_writel(0xffffffff, IC1_CFG0CLR); au_sync();
-	au_writel(sleep_intctl_config0[1], IC1_CFG0SET); au_sync();
-	au_writel(0xffffffff, IC1_CFG1CLR); au_sync();
-	au_writel(sleep_intctl_config1[1], IC1_CFG1SET); au_sync();
-	au_writel(0xffffffff, IC1_CFG2CLR); au_sync();
-	au_writel(sleep_intctl_config2[1], IC1_CFG2SET); au_sync();
-	au_writel(0xffffffff, IC1_SRCCLR); au_sync();
-	au_writel(sleep_intctl_src[1], IC1_SRCSET); au_sync();
-	au_writel(0xffffffff, IC1_ASSIGNCLR); au_sync();
-	au_writel(sleep_intctl_assign[1], IC1_ASSIGNSET); au_sync();
-	au_writel(0xffffffff, IC1_WAKECLR); au_sync();
-	au_writel(sleep_intctl_wake[1], IC1_WAKESET); au_sync();
-	au_writel(0xffffffff, IC1_RISINGCLR); au_sync();
-	au_writel(0xffffffff, IC1_FALLINGCLR); au_sync();
-	au_writel(0x00000000, IC1_TESTBIT); au_sync();
-
-	au_writel(sleep_intctl_mask[1], IC1_MASKSET); au_sync();
-
-	au_writel(sleep_intctl_mask[0], IC0_MASKSET); au_sync();
-}
-#endif /* CONFIG_PM */
-
-
 static void au1x_ic0_unmask(unsigned int irq_nr)
 {
 	unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE;
@@ -635,3 +552,114 @@ void __init arch_init_irq(void)
 		break;
 	}
 }
+
+struct alchemy_ic_sysdev {
+	struct sys_device sysdev;
+	unsigned long pmdata[7 * 2];
+};
+
+static int alchemy_ic_suspend(struct sys_device *dev, pm_message_t state)
+{
+	struct alchemy_ic_sysdev *icdev =
+			container_of(dev, struct alchemy_ic_sysdev, sysdev);
+
+	icdev->pmdata[ 0] = au_readl(IC0_CFG0RD);
+	icdev->pmdata[ 1] = au_readl(IC0_CFG1RD);
+	icdev->pmdata[ 2] = au_readl(IC0_CFG2RD);
+	icdev->pmdata[ 3] = au_readl(IC0_SRCRD);
+	icdev->pmdata[ 4] = au_readl(IC0_ASSIGNRD);
+	icdev->pmdata[ 5] = au_readl(IC0_WAKERD);
+	icdev->pmdata[ 6] = au_readl(IC0_MASKRD);
+
+	icdev->pmdata[ 7] = au_readl(IC1_CFG0RD);
+	icdev->pmdata[ 8] = au_readl(IC1_CFG1RD);
+	icdev->pmdata[ 9] = au_readl(IC1_CFG2RD);
+	icdev->pmdata[10] = au_readl(IC1_SRCRD);
+	icdev->pmdata[11] = au_readl(IC1_ASSIGNRD);
+	icdev->pmdata[12] = au_readl(IC1_WAKERD);
+	icdev->pmdata[13] = au_readl(IC1_MASKRD);
+
+	return 0;
+}
+
+static int alchemy_ic_resume(struct sys_device *dev)
+{
+	struct alchemy_ic_sysdev *icdev =
+			container_of(dev, struct alchemy_ic_sysdev, sysdev);
+
+	au_writel(0xffffffff, IC0_MASKCLR);
+	au_writel(0xffffffff, IC0_CFG0CLR);
+	au_writel(0xffffffff, IC0_CFG1CLR);
+	au_writel(0xffffffff, IC0_CFG2CLR);
+	au_writel(0xffffffff, IC0_SRCCLR);
+	au_writel(0xffffffff, IC0_ASSIGNCLR);
+	au_writel(0xffffffff, IC0_WAKECLR);
+	au_writel(0xffffffff, IC0_RISINGCLR);
+	au_writel(0xffffffff, IC0_FALLINGCLR);
+	au_writel(0x00000000, IC0_TESTBIT);
+	au_sync();
+	au_writel(icdev->pmdata[ 0], IC0_CFG0SET);
+	au_writel(icdev->pmdata[ 1], IC0_CFG1SET);
+	au_writel(icdev->pmdata[ 2], IC0_CFG2SET);
+	au_writel(icdev->pmdata[ 3], IC0_SRCSET);
+	au_writel(icdev->pmdata[ 4], IC0_ASSIGNSET);
+	au_writel(icdev->pmdata[ 5], IC0_WAKESET);
+	au_sync();
+
+	au_writel(0xffffffff, IC1_MASKCLR);
+	au_writel(0xffffffff, IC1_CFG0CLR);
+	au_writel(0xffffffff, IC1_CFG1CLR);
+	au_writel(0xffffffff, IC1_CFG2CLR);
+	au_writel(0xffffffff, IC1_SRCCLR);
+	au_writel(0xffffffff, IC1_ASSIGNCLR);
+	au_writel(0xffffffff, IC1_WAKECLR);
+	au_writel(0xffffffff, IC1_RISINGCLR);
+	au_writel(0xffffffff, IC1_FALLINGCLR);
+	au_writel(0x00000000, IC1_TESTBIT);
+	au_sync();
+	au_writel(icdev->pmdata[ 7], IC1_CFG0SET);
+	au_writel(icdev->pmdata[ 8], IC1_CFG1SET);
+	au_writel(icdev->pmdata[ 9], IC1_CFG2SET);
+	au_writel(icdev->pmdata[10], IC1_SRCSET);
+	au_writel(icdev->pmdata[11], IC1_ASSIGNSET);
+	au_writel(icdev->pmdata[12], IC1_WAKESET);
+	au_sync();
+
+	au_writel(icdev->pmdata[13], IC1_MASKSET);
+	au_sync();
+	au_writel(icdev->pmdata[ 6], IC0_MASKSET);
+	au_sync();
+
+	return 0;
+}
+
+static struct sysdev_class alchemy_ic_sysdev_class = {
+	.name		= "ic",
+	.suspend	= alchemy_ic_suspend,
+	.resume		= alchemy_ic_resume,
+};
+
+static int __init alchemy_ic_sysdev_init(void)
+{
+	struct alchemy_ic_sysdev *icdev;
+	int err;
+
+	icdev = kzalloc(sizeof(struct alchemy_ic_sysdev), GFP_KERNEL);
+	if (!icdev)
+		return -ENOMEM;
+
+	err = sysdev_class_register(&alchemy_ic_sysdev_class);
+	if (err) {
+		kfree(icdev);
+		return err;
+	}
+
+	icdev->sysdev.id = 0;
+	icdev->sysdev.cls = &alchemy_ic_sysdev_class;
+	err = sysdev_register(&icdev->sysdev);
+	if (err)
+		kfree(icdev);
+
+	return err;
+}
+device_initcall(alchemy_ic_sysdev_init);
diff --git a/arch/mips/alchemy/common/power.c b/arch/mips/alchemy/common/power.c
index c07101c..e097094 100644
--- a/arch/mips/alchemy/common/power.c
+++ b/arch/mips/alchemy/common/power.c
@@ -106,9 +106,6 @@ static void save_core_regs(void)
 	sleep_usb[1] = au_readl(0xb4020024);	/* OTG_MUX */
 #endif
 
-	/* Save interrupt controller state. */
-	save_au1xxx_intctl();
-
 	/* Clocks and PLLs. */
 	sleep_sys_clocks[0] = au_readl(SYS_FREQCTRL0);
 	sleep_sys_clocks[1] = au_readl(SYS_FREQCTRL1);
@@ -200,8 +197,6 @@ static void restore_core_regs(void)
 		au_writel(sleep_uart0_clkdiv, UART0_ADDR + UART_CLK); au_sync();
 	}
 
-	restore_au1xxx_intctl();
-
 #if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
 	au1xxx_dbdma_resume();
 #endif
diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h
index cb91714..c84fcd6 100644
--- a/arch/mips/include/asm/mach-au1x00/au1000.h
+++ b/arch/mips/include/asm/mach-au1x00/au1000.h
@@ -191,8 +191,6 @@ extern unsigned long au1xxx_calc_clock(void);
 void alchemy_sleep_au1000(void);
 void alchemy_sleep_au1550(void);
 void au_sleep(void);
-void save_au1xxx_intctl(void);
-void restore_au1xxx_intctl(void);
 
 
 /* SOC Interrupt numbers */
-- 
1.7.0.2

Re: [RFC PATCH] MIPS: Alchemy: add sysdev for both irq controllers

[Ralf Baechle]

On Mon, Mar 08, 2010 at 08:23:00PM +0100, Manuel Lauss wrote:

> From: Manuel Lauss <mano@roarinelk.homelinux.net>
> 
> Use a sysdev to implement PM methods for the Au1000 interrupt controllers.
> 
> Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com>
> ---
> Works on DB1200, not sure though whether this is the correct approach. 
> Applies cleanly only on top of "sleepcode-without-compile-time-cputype"
> patch.

At a quick glance this looks good but since you marked your patch as RFC
I'll do the same in patchwork (http://patchwork.linux-mips.org/patch/1039/)
until you ask me to queue it or resubmit.

Thanks,

  Ralf

Re: [RFC PATCH] MIPS: Alchemy: add sysdev for both irq controllers

[Manuel Lauss]

On Wed, Mar 10, 2010 at 5:13 PM, Ralf Baechle <ralf@linux-mips.org> wrote:
> On Mon, Mar 08, 2010 at 08:23:00PM +0100, Manuel Lauss wrote:
>
>> From: Manuel Lauss <mano@roarinelk.homelinux.net>
>>
>> Use a sysdev to implement PM methods for the Au1000 interrupt controllers.
>>
>> Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com>
>> ---
>> Works on DB1200, not sure though whether this is the correct approach.
>> Applies cleanly only on top of "sleepcode-without-compile-time-cputype"
>> patch.
>
> At a quick glance this looks good but since you marked your patch as RFC
> I'll do the same in patchwork (http://patchwork.linux-mips.org/patch/1039/)
> until you ask me to queue it or resubmit.

I'll resend a refined version.

Manuel

[PATCH] MIPS: Alchemy: move MMC driver registration to board code.

[Manuel Lauss]

Where it really belongs to.

Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com>
---
 arch/mips/alchemy/common/platform.c           |   81 -------------------------
 arch/mips/alchemy/devboards/db1200/platform.c |   48 +++++++++++++--
 arch/mips/alchemy/devboards/pb1200/platform.c |   79 +++++++++++++++++++++++-
 3 files changed, 119 insertions(+), 89 deletions(-)

diff --git a/arch/mips/alchemy/common/platform.c b/arch/mips/alchemy/common/platform.c
index 2580e77..e1ed1ad 100644
--- a/arch/mips/alchemy/common/platform.c
+++ b/arch/mips/alchemy/common/platform.c
@@ -18,7 +18,6 @@
 
 #include <asm/mach-au1x00/au1xxx.h>
 #include <asm/mach-au1x00/au1xxx_dbdma.h>
-#include <asm/mach-au1x00/au1100_mmc.h>
 #include <asm/mach-au1x00/au1xxx_eth.h>
 
 #define PORT(_base, _irq)					\
@@ -231,82 +230,6 @@ static struct platform_device au1200_lcd_device = {
 	.num_resources  = ARRAY_SIZE(au1200_lcd_resources),
 	.resource       = au1200_lcd_resources,
 };
-
-static u64 au1xxx_mmc_dmamask =  DMA_BIT_MASK(32);
-
-extern struct au1xmmc_platform_data au1xmmc_platdata[2];
-
-static struct resource au1200_mmc0_resources[] = {
-	[0] = {
-		.start          = SD0_PHYS_ADDR,
-		.end            = SD0_PHYS_ADDR + 0x7ffff,
-		.flags          = IORESOURCE_MEM,
-	},
-	[1] = {
-		.start		= AU1200_SD_INT,
-		.end		= AU1200_SD_INT,
-		.flags		= IORESOURCE_IRQ,
-	},
-	[2] = {
-		.start		= DSCR_CMD0_SDMS_TX0,
-		.end		= DSCR_CMD0_SDMS_TX0,
-		.flags		= IORESOURCE_DMA,
-	},
-	[3] = {
-		.start          = DSCR_CMD0_SDMS_RX0,
-		.end		= DSCR_CMD0_SDMS_RX0,
-		.flags          = IORESOURCE_DMA,
-	}
-};
-
-static struct platform_device au1200_mmc0_device = {
-	.name = "au1xxx-mmc",
-	.id = 0,
-	.dev = {
-		.dma_mask		= &au1xxx_mmc_dmamask,
-		.coherent_dma_mask	= DMA_BIT_MASK(32),
-		.platform_data		= &au1xmmc_platdata[0],
-	},
-	.num_resources	= ARRAY_SIZE(au1200_mmc0_resources),
-	.resource	= au1200_mmc0_resources,
-};
-
-#ifndef CONFIG_MIPS_DB1200
-static struct resource au1200_mmc1_resources[] = {
-	[0] = {
-		.start          = SD1_PHYS_ADDR,
-		.end            = SD1_PHYS_ADDR + 0x7ffff,
-		.flags          = IORESOURCE_MEM,
-	},
-	[1] = {
-		.start		= AU1200_SD_INT,
-		.end		= AU1200_SD_INT,
-		.flags		= IORESOURCE_IRQ,
-	},
-	[2] = {
-		.start		= DSCR_CMD0_SDMS_TX1,
-		.end		= DSCR_CMD0_SDMS_TX1,
-		.flags		= IORESOURCE_DMA,
-	},
-	[3] = {
-		.start          = DSCR_CMD0_SDMS_RX1,
-		.end		= DSCR_CMD0_SDMS_RX1,
-		.flags          = IORESOURCE_DMA,
-	}
-};
-
-static struct platform_device au1200_mmc1_device = {
-	.name = "au1xxx-mmc",
-	.id = 1,
-	.dev = {
-		.dma_mask		= &au1xxx_mmc_dmamask,
-		.coherent_dma_mask	= DMA_BIT_MASK(32),
-		.platform_data		= &au1xmmc_platdata[1],
-	},
-	.num_resources	= ARRAY_SIZE(au1200_mmc1_resources),
-	.resource	= au1200_mmc1_resources,
-};
-#endif /* #ifndef CONFIG_MIPS_DB1200 */
 #endif /* #ifdef CONFIG_SOC_AU1200 */
 
 /* All Alchemy demoboards with I2C have this #define in their headers */
@@ -421,10 +344,6 @@ static struct platform_device *au1xxx_platform_devices[] __initdata = {
 	&au1xxx_usb_gdt_device,
 	&au1xxx_usb_otg_device,
 	&au1200_lcd_device,
-	&au1200_mmc0_device,
-#ifndef CONFIG_MIPS_DB1200
-	&au1200_mmc1_device,
-#endif
 #endif
 #ifdef SMBUS_PSC_BASE
 	&pbdb_smbus_device,
diff --git a/arch/mips/alchemy/devboards/db1200/platform.c b/arch/mips/alchemy/devboards/db1200/platform.c
index 3cb95a9..9afb287 100644
--- a/arch/mips/alchemy/devboards/db1200/platform.c
+++ b/arch/mips/alchemy/devboards/db1200/platform.c
@@ -329,14 +329,49 @@ static struct led_classdev db1200_mmc_led = {
 };
 
 /* needed by arch/mips/alchemy/common/platform.c */
-struct au1xmmc_platform_data au1xmmc_platdata[] = {
+static struct au1xmmc_platform_data db1200_mmc_platdata = {
+	.cd_setup	= db1200_mmc_cd_setup,
+	.set_power	= db1200_mmc_set_power,
+	.card_inserted	= db1200_mmc_card_inserted,
+	.card_readonly	= db1200_mmc_card_readonly,
+	.led		= &db1200_mmc_led,
+};
+
+static u64 au1xxx_mmc_dmamask =  DMA_BIT_MASK(32);
+
+static struct resource au1200_mmc0_resources[] = {
 	[0] = {
-		.cd_setup	= db1200_mmc_cd_setup,
-		.set_power	= db1200_mmc_set_power,
-		.card_inserted	= db1200_mmc_card_inserted,
-		.card_readonly	= db1200_mmc_card_readonly,
-		.led		= &db1200_mmc_led,
+		.start          = SD0_PHYS_ADDR,
+		.end            = SD0_PHYS_ADDR + 0x7ffff,
+		.flags          = IORESOURCE_MEM,
+	},
+	[1] = {
+		.start		= AU1200_SD_INT,
+		.end		= AU1200_SD_INT,
+		.flags		= IORESOURCE_IRQ,
+	},
+	[2] = {
+		.start		= DSCR_CMD0_SDMS_TX0,
+		.end		= DSCR_CMD0_SDMS_TX0,
+		.flags		= IORESOURCE_DMA,
+	},
+	[3] = {
+		.start          = DSCR_CMD0_SDMS_RX0,
+		.end		= DSCR_CMD0_SDMS_RX0,
+		.flags          = IORESOURCE_DMA,
+	}
+};
+
+static struct platform_device db1200_mmc0_dev = {
+	.name = "au1xxx-mmc",
+	.id = 0,
+	.dev = {
+		.dma_mask		= &au1xxx_mmc_dmamask,
+		.coherent_dma_mask	= DMA_BIT_MASK(32),
+		.platform_data		= &db1200_mmc_platdata,
 	},
+	.num_resources	= ARRAY_SIZE(au1200_mmc0_resources),
+	.resource	= au1200_mmc0_resources,
 };
 
 /**********************************************************************/
@@ -436,6 +471,7 @@ static struct platform_device *db1200_devs[] __initdata = {
 	&db1200_rtc_dev,
 	&db1200_nand_dev,
 	&db1200_audio_dev,
+	&db1200_mmc0_dev,
 };
 
 static int __init db1200_dev_init(void)
diff --git a/arch/mips/alchemy/devboards/pb1200/platform.c b/arch/mips/alchemy/devboards/pb1200/platform.c
index 3ef2dce..89e6f1d 100644
--- a/arch/mips/alchemy/devboards/pb1200/platform.c
+++ b/arch/mips/alchemy/devboards/pb1200/platform.c
@@ -25,6 +25,7 @@
 #include <linux/smc91x.h>
 
 #include <asm/mach-au1x00/au1xxx.h>
+#include <asm/mach-au1x00/au1xxx_dbdma.h>
 #include <asm/mach-au1x00/au1100_mmc.h>
 #include <asm/mach-db1x00/bcsr.h>
 
@@ -88,7 +89,7 @@ static int pb1200mmc1_card_inserted(void *mmc_host)
 	return (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD1INSERT) ? 1 : 0;
 }
 
-const struct au1xmmc_platform_data au1xmmc_platdata[2] = {
+static struct au1xmmc_platform_data pb1200_mmc_platdata[2] = {
 	[0] = {
 		.set_power	= pb1200mmc0_set_power,
 		.card_inserted	= pb1200mmc0_card_inserted,
@@ -105,6 +106,78 @@ const struct au1xmmc_platform_data au1xmmc_platdata[2] = {
 	},
 };
 
+static u64 au1xxx_mmc_dmamask =  DMA_BIT_MASK(32);
+
+static struct resource au1200_mmc0_resources[] = {
+	[0] = {
+		.start          = SD0_PHYS_ADDR,
+		.end            = SD0_PHYS_ADDR + 0x7ffff,
+		.flags          = IORESOURCE_MEM,
+	},
+	[1] = {
+		.start		= AU1200_SD_INT,
+		.end		= AU1200_SD_INT,
+		.flags		= IORESOURCE_IRQ,
+	},
+	[2] = {
+		.start		= DSCR_CMD0_SDMS_TX0,
+		.end		= DSCR_CMD0_SDMS_TX0,
+		.flags		= IORESOURCE_DMA,
+	},
+	[3] = {
+		.start          = DSCR_CMD0_SDMS_RX0,
+		.end		= DSCR_CMD0_SDMS_RX0,
+		.flags          = IORESOURCE_DMA,
+	}
+};
+
+static struct platform_device pb1200_mmc0_device = {
+	.name = "au1xxx-mmc",
+	.id = 0,
+	.dev = {
+		.dma_mask		= &au1xxx_mmc_dmamask,
+		.coherent_dma_mask	= DMA_BIT_MASK(32),
+		.platform_data		= &pb1200_mmc_platdata[0],
+	},
+	.num_resources	= ARRAY_SIZE(au1200_mmc0_resources),
+	.resource	= au1200_mmc0_resources,
+};
+
+static struct resource au1200_mmc1_resources[] = {
+	[0] = {
+		.start          = SD1_PHYS_ADDR,
+		.end            = SD1_PHYS_ADDR + 0x7ffff,
+		.flags          = IORESOURCE_MEM,
+	},
+	[1] = {
+		.start		= AU1200_SD_INT,
+		.end		= AU1200_SD_INT,
+		.flags		= IORESOURCE_IRQ,
+	},
+	[2] = {
+		.start		= DSCR_CMD0_SDMS_TX1,
+		.end		= DSCR_CMD0_SDMS_TX1,
+		.flags		= IORESOURCE_DMA,
+	},
+	[3] = {
+		.start          = DSCR_CMD0_SDMS_RX1,
+		.end		= DSCR_CMD0_SDMS_RX1,
+		.flags          = IORESOURCE_DMA,
+	}
+};
+
+static struct platform_device pb1200_mmc1_device = {
+	.name = "au1xxx-mmc",
+	.id = 1,
+	.dev = {
+		.dma_mask		= &au1xxx_mmc_dmamask,
+		.coherent_dma_mask	= DMA_BIT_MASK(32),
+		.platform_data		= &pb1200_mmc_platdata[1],
+	},
+	.num_resources	= ARRAY_SIZE(au1200_mmc1_resources),
+	.resource	= au1200_mmc1_resources,
+};
+
 static struct resource ide_resources[] = {
 	[0] = {
 		.start	= IDE_PHYS_ADDR,
@@ -163,7 +236,9 @@ static struct platform_device smc91c111_device = {
 
 static struct platform_device *board_platform_devices[] __initdata = {
 	&ide_device,
-	&smc91c111_device
+	&smc91c111_device,
+	&pb1200_mmc0_device,
+	&pb1200_mmc1_device
 };
 
 static int __init board_register_devices(void)
-- 
1.7.0.2

Re: [PATCH] MIPS: Alchemy: move MMC driver registration to board code.

[Sergei Shtylyov]

Hello.

Manuel Lauss wrote:

> Where it really belongs to.
>   

   I disagree (again). SoC platform devices dont belong with the board code.

WBR, Sergei

Re: [PATCH] MIPS: Alchemy: move MMC driver registration to board code.

[Manuel Lauss]

On Tue, Mar 9, 2010 at 12:33 PM, Sergei Shtylyov <sshtylyov@mvista.com> wrote:
> Hello.
>
> Manuel Lauss wrote:
>
>> Where it really belongs to.
>>
>
>  I disagree (again). SoC platform devices dont belong with the board code.

Figured as much.  However with additional boards the #ifdef mess in
common/platform.c
is only going to get worse. MUCH worse. Just look at the au1000-eth
platform data situation!
I have these platform devices on Au1200/Au1300 even thought they don't have
a built-in MAC.

The board which uses the device should register it.  The UARTs are
kind of a special
case since they need to be fixed up with the correct busclock, but
that too could be
exported to an initialization wrapper.

But, consider the patch withdrawn.

Manuel

Re: [PATCH] MIPS: Alchemy: move MMC driver registration to board code.

[Manuel Lauss]

On Tue, Mar 9, 2010 at 12:33 PM, Sergei Shtylyov <sshtylyov@mvista.com> wrote:
> Hello.
>
> Manuel Lauss wrote:
>
>> Where it really belongs to.
>>
>
>  I disagree (again). SoC platform devices dont belong with the board code.

Figured as much.  However with additional boards the #ifdef mess in
common/platform.c
is only going to get worse. MUCH worse. Just look at the au1000-eth
platform data situation!
I have these platform devices on Au1200/Au1300 even thought they don't have
a built-in MAC.

The board which uses the device should register it.  The UARTs are
kind of a special
case since they need to be fixed up with the correct busclock, but
that too could be
exported to an initialization wrapper.

But, consider the patch withdrawn.

Manuel

Re: [PATCH] MIPS: Alchemy: move MMC driver registration to board code.

[Sergei Shtylyov]

Manuel Lauss wrote:

>>> Where it really belongs to.
>> I disagree (again). SoC platform devices dont belong with the board code.
>>     
>
> Figured as much.  However with additional boards the #ifdef mess in
> common/platform.c
> is only going to get worse. MUCH worse.

   We could probably eliminate the board #ifdef in platfrom.c by not 
supplying the platfrom data for MMC1.

> Just look at the au1000-eth platform data situation!
> I have these platform devices on Au1200/Au1300 even thought they don't have
> a built-in MAC.
>   

   Need to add the SoC type checks then when registering the devices. Or 
at least the #ifdef's. :-)

> The board which uses the device should register it.

   Contrarywise, the SoC that has the devices, should register them.

> But, consider the patch withdrawn.
>   

   Thanks.

> Manuel
>   

WBR, Sergei

Re: [PATCH] MIPS: Alchemy: move MMC driver registration to board code.

[Manuel Lauss]

On Tue, Mar 9, 2010 at 12:51 PM, Sergei Shtylyov <sshtylyov@mvista.com> wrote:
> Manuel Lauss wrote:
>
>>>> Where it really belongs to.
>>>
>>> I disagree (again). SoC platform devices dont belong with the board code.
>>>
>>
>> Figured as much.  However with additional boards the #ifdef mess in
>> common/platform.c
>> is only going to get worse. MUCH worse.
>
>  We could probably eliminate the board #ifdef in platfrom.c by not supplying
> the platfrom data for MMC1.

What if I wanted to build a kernel which supports multiple different
Au1200-based systems, like the SH-port does with its mach vector?


>> Just look at the au1000-eth platform data situation!
>> I have these platform devices on Au1200/Au1300 even thought they don't
>> have
>> a built-in MAC.
>>
>
>  Need to add the SoC type checks then when registering the devices. Or at
> least the #ifdef's. :-)

I'd like to get rid of the ifdefs, not encourage them to mate and multiply ;-)


>> The board which uses the device should register it.
>
>  Contrarywise, the SoC that has the devices, should register them.

My point is that most drivers require additional information from the board, and
maybe due to hardware design the ids may need to be swapped.  Rather than
#ifdeffing these cases for every board in a central file I'd let the board using
the devices sort this out.

In my case, I don't need UART0 of the Au1200, but need UART1 to be ttyS0.

And on a personal note, that file just bothers me.  It's messy, can
cause merge conflicts,
it references structures defined inside board-specific code. In short,
it just plain annoys
my sense of aesthetics.

Manuel

Re: [PATCH] MIPS: Alchemy: move MMC driver registration to board code.

[Manuel Lauss]

On Tue, Mar 9, 2010 at 12:51 PM, Sergei Shtylyov <sshtylyov@mvista.com> wrote:
> Manuel Lauss wrote:
>
>>>> Where it really belongs to.
>>>
>>> I disagree (again). SoC platform devices dont belong with the board code.
>>>
>>
>> Figured as much.  However with additional boards the #ifdef mess in
>> common/platform.c
>> is only going to get worse. MUCH worse.
>
>  We could probably eliminate the board #ifdef in platfrom.c by not supplying
> the platfrom data for MMC1.

What if I wanted to build a kernel which supports multiple different
Au1200-based systems, like the SH-port does with its mach vector?


>> Just look at the au1000-eth platform data situation!
>> I have these platform devices on Au1200/Au1300 even thought they don't
>> have
>> a built-in MAC.
>>
>
>  Need to add the SoC type checks then when registering the devices. Or at
> least the #ifdef's. :-)

I'd like to get rid of the ifdefs, not encourage them to mate and multiply ;-)


>> The board which uses the device should register it.
>
>  Contrarywise, the SoC that has the devices, should register them.

My point is that most drivers require additional information from the board, and
maybe due to hardware design the ids may need to be swapped.  Rather than
#ifdeffing these cases for every board in a central file I'd let the board using
the devices sort this out.

In my case, I don't need UART0 of the Au1200, but need UART1 to be ttyS0.

And on a personal note, that file just bothers me.  It's messy, can
cause merge conflicts,
it references structures defined inside board-specific code. In short,
it just plain annoys
my sense of aesthetics.

Manuel

Re: [PATCH] MIPS: Alchemy: move MMC driver registration to board code.

[Ralf Baechle]

On Tue, Mar 09, 2010 at 01:03:51PM +0100, Manuel Lauss wrote:

> And on a personal note, that file just bothers me.  It's messy, can
> cause merge conflicts,

Eye cancer.

> it references structures defined inside board-specific code. In short,
> it just plain annoys
> my sense of aesthetics.

Indeed - and I don't think Sergej disagrees with that.  I agree with him
that device registration code should primarily be done in the SOC code -
but you'll need to somehow get that code to communicate with the platform
code about what really needs to be done then register the remainder of
the truely platform-specific platform devices.  Something like that.

  Ralf

Re: [PATCH] MIPS: Alchemy: move MMC driver registration to board code.

[Manuel Lauss]

On Wed, Mar 10, 2010 at 5:48 PM, Ralf Baechle <ralf@linux-mips.org> wrote:
> On Tue, Mar 09, 2010 at 01:03:51PM +0100, Manuel Lauss wrote:
>
>> And on a personal note, that file just bothers me.  It's messy, can
>> cause merge conflicts,
>
> Eye cancer.
>
>> it references structures defined inside board-specific code. In short,
>> it just plain annoys
>> my sense of aesthetics.
>
> Indeed - and I don't think Sergej disagrees with that.  I agree with him
> that device registration code should primarily be done in the SOC code -

For things like fixed internal interrupts, sure.  But for pieces that depend
on where the (and which) chip is used, not so much.

By this logic there should be tons of ifdefs in the interrupt tables for every
in-tree board.


> but you'll need to somehow get that code to communicate with the platform
> code about what really needs to be done then register the remainder of
> the truely platform-specific platform devices.  Something like that.

I prefer a simpler solution.

Manuel

Re: [PATCH] MIPS: Alchemy: move MMC driver registration to board code.

[Manuel Lauss]

On Wed, Mar 10, 2010 at 5:48 PM, Ralf Baechle <ralf@linux-mips.org> wrote:
> On Tue, Mar 09, 2010 at 01:03:51PM +0100, Manuel Lauss wrote:
>
>> And on a personal note, that file just bothers me.  It's messy, can
>> cause merge conflicts,
>
> Eye cancer.
>
>> it references structures defined inside board-specific code. In short,
>> it just plain annoys
>> my sense of aesthetics.
>
> Indeed - and I don't think Sergej disagrees with that.  I agree with him
> that device registration code should primarily be done in the SOC code -

For things like fixed internal interrupts, sure.  But for pieces that depend
on where the (and which) chip is used, not so much.

By this logic there should be tons of ifdefs in the interrupt tables for every
in-tree board.


> but you'll need to somehow get that code to communicate with the platform
> code about what really needs to be done then register the remainder of
> the truely platform-specific platform devices.  Something like that.

I prefer a simpler solution.

Manuel

Re: [PATCH] MIPS: Alchemy: sleepcode without compile-time cputype dependencies

[Ralf Baechle]

On Mon, Mar 08, 2010 at 08:22:59PM +0100, Manuel Lauss wrote:

> Split the low-level sleepcode into per-memory-controller-generation
> functions and figure out which one to call at runtime instead of
> relying on compile-time-defined cpu types.
> 
> Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com>

Thanks, queued for 2.6.35.

  Ralf