From: Mark Brown <broonie@opensource.wolfsonmicro.com>
To: Jarkko Nikula <jhnikula@gmail.com>
Cc: alsa-devel@alsa-project.org, Liam Girdwood <lrg@slimlogic.co.uk>
Subject: Re: [PATCH 3/3] ASoC: tlv320aic3x: Complete the soc-cache conversion
Date: Tue, 14 Sep 2010 13:55:10 +0100 [thread overview]
Message-ID: <20100914125510.GA21715@rakim.wolfsonmicro.main> (raw)
In-Reply-To: <20100914154525.77e86440.jhnikula@gmail.com>
On Tue, Sep 14, 2010 at 03:45:25PM +0300, Jarkko Nikula wrote:
> But is it marking register as volatile due 1-2 bits causing more
> problems if we don't cache rest of the r/w bits?
Depends on what else is there - ultimately if the chip has read support
then the register cache is just a performance improvement.
next prev parent reply other threads:[~2010-09-14 12:55 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-09-14 11:54 [PATCH 1/3] ASoC: tlv320aic3x: Use snd_soc_read and snd_soc_write Jarkko Nikula
2010-09-14 11:54 ` [PATCH 2/3] ASoC: tlv320aic3x: Switch to soc-cache helpers Jarkko Nikula
2010-09-14 11:59 ` Mark Brown
2010-09-14 11:54 ` [PATCH 3/3] ASoC: tlv320aic3x: Complete the soc-cache conversion Jarkko Nikula
2010-09-14 12:04 ` Mark Brown
2010-09-14 12:14 ` Jarkko Nikula
2010-09-14 12:21 ` Mark Brown
2010-09-14 12:45 ` Jarkko Nikula
2010-09-14 12:55 ` Mark Brown [this message]
2010-09-14 13:59 ` [PATCHv2 " Jarkko Nikula
2010-09-14 15:08 ` Mark Brown
2010-09-15 12:57 ` Liam Girdwood
2010-09-14 11:59 ` [PATCH 1/3] ASoC: tlv320aic3x: Use snd_soc_read and snd_soc_write Mark Brown
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