* [PATCH] drm/i915: skip FDI & PCH enabling for DP_A
@ 2011-01-05 18:31 Jesse Barnes
2011-01-06 1:42 ` Yuanhan Liu
2011-01-06 1:43 ` Zhenyu Wang
0 siblings, 2 replies; 6+ messages in thread
From: Jesse Barnes @ 2011-01-05 18:31 UTC (permalink / raw)
To: intel-gfx
eDP on the CPU doesn't need the PCH set up at all, it can in fact cause
problems. So avoid FDI training and PCH PLL enabling in that case.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
drivers/gpu/drm/i915/intel_display.c | 97 +++++++++++++++++++++-------------
1 files changed, 60 insertions(+), 37 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 395acb8..2441a00 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2616,49 +2616,21 @@ static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
return true;
}
-static void ironlake_crtc_enable(struct drm_crtc *crtc)
+/*
+ * Enable PCH resources required for PCH ports:
+ * - PCH PLLs
+ * - FDI training & RX/TX
+ * - update transcoder timings
+ * - DP transcoding bits
+ * - transcoder
+ */
+static void ironlake_pch_enable(struct drm_crtc *crtc)
{
struct drm_device *dev = crtc->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
int pipe = intel_crtc->pipe;
- int plane = intel_crtc->plane;
u32 reg, temp;
- bool is_pch_port;
-
- if (intel_crtc->active)
- return;
-
- intel_crtc->active = true;
- intel_update_watermarks(dev);
-
- if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
- temp = I915_READ(PCH_LVDS);
- if ((temp & LVDS_PORT_EN) == 0)
- I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
- }
-
- ironlake_fdi_enable(crtc);
-
- /* Enable panel fitting for LVDS */
- if (dev_priv->pch_pf_size &&
- (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
- /* Force use of hard-coded filter coefficients
- * as some pre-programmed values are broken,
- * e.g. x201.
- */
- I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1,
- PF_ENABLE | PF_FILTER_MED_3x3);
- I915_WRITE(pipe ? PFB_WIN_POS : PFA_WIN_POS,
- dev_priv->pch_pf_pos);
- I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ,
- dev_priv->pch_pf_size);
- }
-
- is_pch_port = intel_crtc_driving_pch(crtc);
-
- intel_enable_pipe(dev_priv, pipe, is_pch_port);
- intel_enable_plane(dev_priv, plane, pipe);
/* For PCH output, training FDI link */
if (IS_GEN6(dev))
@@ -2727,6 +2699,57 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
}
intel_enable_transcoder(dev_priv, pipe);
+}
+
+static void ironlake_crtc_enable(struct drm_crtc *crtc)
+{
+ struct drm_device *dev = crtc->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ int pipe = intel_crtc->pipe;
+ int plane = intel_crtc->plane;
+ u32 temp;
+ bool is_pch_port;
+
+ if (intel_crtc->active)
+ return;
+
+ intel_crtc->active = true;
+ intel_update_watermarks(dev);
+
+ if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
+ temp = I915_READ(PCH_LVDS);
+ if ((temp & LVDS_PORT_EN) == 0)
+ I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
+ }
+
+ is_pch_port = intel_crtc_driving_pch(crtc);
+
+ if (is_pch_port)
+ ironlake_fdi_enable(crtc);
+ else
+ ironlake_fdi_disable(crtc);
+
+ /* Enable panel fitting for LVDS */
+ if (dev_priv->pch_pf_size &&
+ (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
+ /* Force use of hard-coded filter coefficients
+ * as some pre-programmed values are broken,
+ * e.g. x201.
+ */
+ I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1,
+ PF_ENABLE | PF_FILTER_MED_3x3);
+ I915_WRITE(pipe ? PFB_WIN_POS : PFA_WIN_POS,
+ dev_priv->pch_pf_pos);
+ I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ,
+ dev_priv->pch_pf_size);
+ }
+
+ intel_enable_pipe(dev_priv, pipe, is_pch_port);
+ intel_enable_plane(dev_priv, plane, pipe);
+
+ if (is_pch_port)
+ ironlake_pch_enable(crtc);
intel_crtc_load_lut(crtc);
intel_update_fbc(dev);
--
1.7.0.4
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH] drm/i915: skip FDI & PCH enabling for DP_A
2011-01-05 18:31 [PATCH] drm/i915: skip FDI & PCH enabling for DP_A Jesse Barnes
@ 2011-01-06 1:42 ` Yuanhan Liu
2011-01-06 9:19 ` Yuanhan Liu
2011-01-06 1:43 ` Zhenyu Wang
1 sibling, 1 reply; 6+ messages in thread
From: Yuanhan Liu @ 2011-01-06 1:42 UTC (permalink / raw)
To: Jesse Barnes; +Cc: intel-gfx
On Wed, Jan 05, 2011 at 10:31:48AM -0800, Jesse Barnes wrote:
> eDP on the CPU doesn't need the PCH set up at all, it can in fact cause
> problems. So avoid FDI training and PCH PLL enabling in that case.
Hey, skip PCH set up on eDP does fix the bug 29791(eDP blank screen issue).
Well, I didn't test with this patch, as it depends on the serial patches
you send before(I would like to have a test today). I just made up a simple
patch to skip PCH set up if HAS_eDP is met.
Thanks,
Yuanhan Liu
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] drm/i915: skip FDI & PCH enabling for DP_A
2011-01-06 1:42 ` Yuanhan Liu
@ 2011-01-06 9:19 ` Yuanhan Liu
0 siblings, 0 replies; 6+ messages in thread
From: Yuanhan Liu @ 2011-01-06 9:19 UTC (permalink / raw)
To: Jesse Barnes; +Cc: intel-gfx
On Thu, Jan 06, 2011 at 09:42:26AM +0800, Yuanhan Liu wrote:
> On Wed, Jan 05, 2011 at 10:31:48AM -0800, Jesse Barnes wrote:
> > eDP on the CPU doesn't need the PCH set up at all, it can in fact cause
> > problems. So avoid FDI training and PCH PLL enabling in that case.
>
> Hey, skip PCH set up on eDP does fix the bug 29791(eDP blank screen issue).
>
> Well, I didn't test with this patch, as it depends on the serial patches
> you send before(I would like to have a test today).
Tested, and worked well. So,
Tested-by: Yuanhan Liu <yuanhan.liu@linux.intel.com>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] drm/i915: skip FDI & PCH enabling for DP_A
2011-01-05 18:31 [PATCH] drm/i915: skip FDI & PCH enabling for DP_A Jesse Barnes
2011-01-06 1:42 ` Yuanhan Liu
@ 2011-01-06 1:43 ` Zhenyu Wang
1 sibling, 0 replies; 6+ messages in thread
From: Zhenyu Wang @ 2011-01-06 1:43 UTC (permalink / raw)
To: Jesse Barnes; +Cc: intel-gfx, Liu, Yuanhan
[-- Attachment #1.1: Type: text/plain, Size: 4620 bytes --]
On 2011.01.05 10:31:48 -0800, Jesse Barnes wrote:
> eDP on the CPU doesn't need the PCH set up at all, it can in fact cause
> problems. So avoid FDI training and PCH PLL enabling in that case.
>
Right, I think that's what I did during early eDP enabling.
Yuanhan, please test this on sandybridge eDP panel.
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> ---
> drivers/gpu/drm/i915/intel_display.c | 97 +++++++++++++++++++++-------------
> 1 files changed, 60 insertions(+), 37 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 395acb8..2441a00 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2616,49 +2616,21 @@ static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
> return true;
> }
>
> -static void ironlake_crtc_enable(struct drm_crtc *crtc)
> +/*
> + * Enable PCH resources required for PCH ports:
> + * - PCH PLLs
> + * - FDI training & RX/TX
> + * - update transcoder timings
> + * - DP transcoding bits
> + * - transcoder
> + */
> +static void ironlake_pch_enable(struct drm_crtc *crtc)
> {
> struct drm_device *dev = crtc->dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> int pipe = intel_crtc->pipe;
> - int plane = intel_crtc->plane;
> u32 reg, temp;
> - bool is_pch_port;
> -
> - if (intel_crtc->active)
> - return;
> -
> - intel_crtc->active = true;
> - intel_update_watermarks(dev);
> -
> - if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
> - temp = I915_READ(PCH_LVDS);
> - if ((temp & LVDS_PORT_EN) == 0)
> - I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
> - }
> -
> - ironlake_fdi_enable(crtc);
> -
> - /* Enable panel fitting for LVDS */
> - if (dev_priv->pch_pf_size &&
> - (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
> - /* Force use of hard-coded filter coefficients
> - * as some pre-programmed values are broken,
> - * e.g. x201.
> - */
> - I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1,
> - PF_ENABLE | PF_FILTER_MED_3x3);
> - I915_WRITE(pipe ? PFB_WIN_POS : PFA_WIN_POS,
> - dev_priv->pch_pf_pos);
> - I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ,
> - dev_priv->pch_pf_size);
> - }
> -
> - is_pch_port = intel_crtc_driving_pch(crtc);
> -
> - intel_enable_pipe(dev_priv, pipe, is_pch_port);
> - intel_enable_plane(dev_priv, plane, pipe);
>
> /* For PCH output, training FDI link */
> if (IS_GEN6(dev))
> @@ -2727,6 +2699,57 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
> }
>
> intel_enable_transcoder(dev_priv, pipe);
> +}
> +
> +static void ironlake_crtc_enable(struct drm_crtc *crtc)
> +{
> + struct drm_device *dev = crtc->dev;
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> + int pipe = intel_crtc->pipe;
> + int plane = intel_crtc->plane;
> + u32 temp;
> + bool is_pch_port;
> +
> + if (intel_crtc->active)
> + return;
> +
> + intel_crtc->active = true;
> + intel_update_watermarks(dev);
> +
> + if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
> + temp = I915_READ(PCH_LVDS);
> + if ((temp & LVDS_PORT_EN) == 0)
> + I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
> + }
> +
> + is_pch_port = intel_crtc_driving_pch(crtc);
> +
> + if (is_pch_port)
> + ironlake_fdi_enable(crtc);
> + else
> + ironlake_fdi_disable(crtc);
> +
> + /* Enable panel fitting for LVDS */
> + if (dev_priv->pch_pf_size &&
> + (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
> + /* Force use of hard-coded filter coefficients
> + * as some pre-programmed values are broken,
> + * e.g. x201.
> + */
> + I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1,
> + PF_ENABLE | PF_FILTER_MED_3x3);
> + I915_WRITE(pipe ? PFB_WIN_POS : PFA_WIN_POS,
> + dev_priv->pch_pf_pos);
> + I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ,
> + dev_priv->pch_pf_size);
> + }
> +
> + intel_enable_pipe(dev_priv, pipe, is_pch_port);
> + intel_enable_plane(dev_priv, plane, pipe);
> +
> + if (is_pch_port)
> + ironlake_pch_enable(crtc);
>
> intel_crtc_load_lut(crtc);
> intel_update_fbc(dev);
> --
> 1.7.0.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Open Source Technology Center, Intel ltd.
$gpg --keyserver wwwkeys.pgp.net --recv-keys 4D781827
[-- Attachment #1.2: Digital signature --]
[-- Type: application/pgp-signature, Size: 198 bytes --]
[-- Attachment #2: Type: text/plain, Size: 159 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH] drm/i915: skip FDI & PCH enabling for DP_A
@ 2011-02-15 23:08 Jesse Barnes
2011-02-15 23:11 ` Jesse Barnes
0 siblings, 1 reply; 6+ messages in thread
From: Jesse Barnes @ 2011-02-15 23:08 UTC (permalink / raw)
To: intel-gfx
eDP on the CPU doesn't need the PCH set up at all, it can in fact cause
problems. So avoid FDI training and PCH PLL enabling in that case.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
drivers/gpu/drm/i915/intel_display.c | 83 +++++++++++++++++++++++++++++++++-
1 files changed, 81 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 7e42aa5..08747ab 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2045,6 +2045,31 @@ static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
atomic_read(&obj->pending_flip) == 0);
}
+static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
+{
+ struct drm_device *dev = crtc->dev;
+ struct drm_mode_config *mode_config = &dev->mode_config;
+ struct intel_encoder *encoder;
+
+ /*
+ * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
+ * must be driven by its own crtc; no sharing is possible.
+ */
+ list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
+ if (encoder->base.crtc != crtc)
+ continue;
+
+ switch (encoder->type) {
+ case INTEL_OUTPUT_EDP:
+ if (!intel_encoder_is_pch_edp(&encoder->base))
+ return false;
+ continue;
+ }
+ }
+
+ return true;
+}
+
static void ironlake_crtc_enable(struct drm_crtc *crtc)
{
struct drm_device *dev = crtc->dev;
@@ -2053,6 +2078,7 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
int pipe = intel_crtc->pipe;
int plane = intel_crtc->plane;
u32 reg, temp;
+ bool is_pch_port = false;
if (intel_crtc->active)
return;
@@ -2066,7 +2092,56 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
}
- ironlake_fdi_enable(crtc);
+ is_pch_port = intel_crtc_driving_pch(crtc);
+
+ if (is_pch_port)
+ ironlake_fdi_enable(crtc);
+ else {
+ /* disable CPU FDI tx and PCH FDI rx */
+ reg = FDI_TX_CTL(pipe);
+ temp = I915_READ(reg);
+ I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
+ POSTING_READ(reg);
+
+ reg = FDI_RX_CTL(pipe);
+ temp = I915_READ(reg);
+ temp &= ~(0x7 << 16);
+ temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
+ I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
+
+ POSTING_READ(reg);
+ udelay(100);
+
+ /* Ironlake workaround, disable clock pointer after downing FDI */
+ if (HAS_PCH_IBX(dev))
+ I915_WRITE(FDI_RX_CHICKEN(pipe),
+ I915_READ(FDI_RX_CHICKEN(pipe) &
+ ~FDI_RX_PHASE_SYNC_POINTER_ENABLE));
+
+ /* still set train pattern 1 */
+ reg = FDI_TX_CTL(pipe);
+ temp = I915_READ(reg);
+ temp &= ~FDI_LINK_TRAIN_NONE;
+ temp |= FDI_LINK_TRAIN_PATTERN_1;
+ I915_WRITE(reg, temp);
+
+ reg = FDI_RX_CTL(pipe);
+ temp = I915_READ(reg);
+ if (HAS_PCH_CPT(dev)) {
+ temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
+ temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
+ } else {
+ temp &= ~FDI_LINK_TRAIN_NONE;
+ temp |= FDI_LINK_TRAIN_PATTERN_1;
+ }
+ /* BPC in FDI rx is consistent with that in PIPECONF */
+ temp &= ~(0x07 << 16);
+ temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
+ I915_WRITE(reg, temp);
+
+ POSTING_READ(reg);
+ udelay(100);
+ }
/* Enable panel fitting for LVDS */
if (dev_priv->pch_pf_size &&
@@ -2100,6 +2175,10 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
intel_flush_display_plane(dev, plane);
}
+ /* Skip the PCH stuff if possible */
+ if (!is_pch_port)
+ goto done;
+
/* For PCH output, training FDI link */
if (IS_GEN6(dev))
gen6_fdi_link_train(crtc);
@@ -2184,7 +2263,7 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
I915_WRITE(reg, temp | TRANS_ENABLE);
if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
DRM_ERROR("failed to enable transcoder %d\n", pipe);
-
+done:
intel_crtc_load_lut(crtc);
intel_update_fbc(dev);
intel_crtc_update_cursor(crtc, true);
--
1.7.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH] drm/i915: skip FDI & PCH enabling for DP_A
2011-02-15 23:08 Jesse Barnes
@ 2011-02-15 23:11 ` Jesse Barnes
0 siblings, 0 replies; 6+ messages in thread
From: Jesse Barnes @ 2011-02-15 23:11 UTC (permalink / raw)
Cc: intel-gfx
On Tue, 15 Feb 2011 15:08:02 -0800
Jesse Barnes <jbarnes@virtuousgeek.org> wrote:
> eDP on the CPU doesn't need the PCH set up at all, it can in fact cause
> problems. So avoid FDI training and PCH PLL enabling in that case.
>
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> ---
Backported with copy & paste to 2.6.38-rc4. Unfortunately
drm-intel-next and Linus's tree have diverged enough that conflicts
will occur when this version is merged with the one in drm-intel-next
again.
--
Jesse Barnes, Intel Open Source Technology Center
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2011-02-15 23:11 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2011-01-05 18:31 [PATCH] drm/i915: skip FDI & PCH enabling for DP_A Jesse Barnes
2011-01-06 1:42 ` Yuanhan Liu
2011-01-06 9:19 ` Yuanhan Liu
2011-01-06 1:43 ` Zhenyu Wang
-- strict thread matches above, loose matches on Subject: below --
2011-02-15 23:08 Jesse Barnes
2011-02-15 23:11 ` Jesse Barnes
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.