* [PATCH V5 1/4] ARM: Xilinx: Adding Xilinx board support [not found] <1301444651-18008-1-git-send-email-john.linn@xilinx.com> @ 2011-03-30 0:24 ` John Linn [not found] ` <1301444651-18008-2-git-send-email-john.linn@xilinx.com> 1 sibling, 0 replies; 22+ messages in thread From: John Linn @ 2011-03-30 0:24 UTC (permalink / raw) To: linux-arm-kernel The 1st board support is minimal to get a system up and running on the Xilinx platform. Signed-off-by: John Linn <john.linn@xilinx.com> --- V5 Changes Minor cleanup based on input from Jamie Iles. Update to work with code in next merge (PLAT_PHYS_OFFSET). V4 Changes Minor cleanup based on input from Jamie Iles. V3 Changes Updates based on Russell Kings' comments Changed headers to update the license info and remove the address Changed the name of functions to include "xilinx" in common.c and common.h Changed the Kconfig and Makefile to use MACH_XILINX which matches the machine registered. V2 Changes Updates based on Russell King's comments minor cleanups cleaned up physical/virtual addresses in early i/o table arch/arm/mach-xilinx/Kconfig | 14 +++++ arch/arm/mach-xilinx/Makefile | 7 ++ arch/arm/mach-xilinx/Makefile.boot | 3 + arch/arm/mach-xilinx/board_ep107.c | 85 +++++++++++++++++++++++++++ arch/arm/mach-xilinx/common.c | 114 ++++++++++++++++++++++++++++++++++++ arch/arm/mach-xilinx/common.h | 30 +++++++++ 6 files changed, 253 insertions(+), 0 deletions(-) create mode 100644 arch/arm/mach-xilinx/Kconfig create mode 100644 arch/arm/mach-xilinx/Makefile create mode 100644 arch/arm/mach-xilinx/Makefile.boot create mode 100644 arch/arm/mach-xilinx/board_ep107.c create mode 100644 arch/arm/mach-xilinx/common.c create mode 100644 arch/arm/mach-xilinx/common.h diff --git a/arch/arm/mach-xilinx/Kconfig b/arch/arm/mach-xilinx/Kconfig new file mode 100644 index 0000000..01181d2 --- /dev/null +++ b/arch/arm/mach-xilinx/Kconfig @@ -0,0 +1,14 @@ +if ARCH_XILINX + +choice + prompt "Board Selection" + default MACH_XILINX_EP107 + +config MACH_XILINX_EP107 + bool "Xilinx EP107 Board" + help + Select if you are using a Xilinx EP107 board. + +endchoice + +endif diff --git a/arch/arm/mach-xilinx/Makefile b/arch/arm/mach-xilinx/Makefile new file mode 100644 index 0000000..19489e7 --- /dev/null +++ b/arch/arm/mach-xilinx/Makefile @@ -0,0 +1,7 @@ +# +# Makefile for the linux kernel. +# + +# Common support +obj-y := common.o +obj-$(CONFIG_MACH_XILINX_EP107) += board_ep107.o diff --git a/arch/arm/mach-xilinx/Makefile.boot b/arch/arm/mach-xilinx/Makefile.boot new file mode 100644 index 0000000..67039c3 --- /dev/null +++ b/arch/arm/mach-xilinx/Makefile.boot @@ -0,0 +1,3 @@ + zreladdr-y := 0x00008000 +params_phys-y := 0x00000100 +initrd_phys-y := 0x00800000 diff --git a/arch/arm/mach-xilinx/board_ep107.c b/arch/arm/mach-xilinx/board_ep107.c new file mode 100644 index 0000000..f6abe3f --- /dev/null +++ b/arch/arm/mach-xilinx/board_ep107.c @@ -0,0 +1,85 @@ +/* arch/arm/mach-xilinx/board_ep107.c + * + * This file contains code specific to the Xilinx EP107 board. + * + * Copyright (C) 2011 Xilinx + * + * based on /arch/arm/mach-realview/core.c + * + * Copyright (C) 1999 - 2003 ARM Limited + * Copyright (C) 2000 Deep Blue Solutions Ltd + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/platform_device.h> +#include <linux/clkdev.h> + +#include <asm/mach-types.h> +#include <asm/mach/arch.h> + +#include <mach/xilinx_soc.h> +#include <mach/irqs.h> +#include <mach/memory.h> +#include "common.h" + +/* + * Fixed clocks for now + */ + +static struct clk ref50_clk = { + .rate = 50000000, +}; + +/* Create all the platform devices for the board */ + +static struct resource uart0[] = { + { + .start = UART0_PHYS, + .end = UART0_PHYS + 0xFFF, + .flags = IORESOURCE_MEM, + }, { + .start = IRQ_UART0, + .end = IRQ_UART0, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device uart_device0 = { + .name = "xuartpss", + .id = 0, + .dev = { + .platform_data = &ref50_clk.rate, + }, + .resource = uart0, + .num_resources = ARRAY_SIZE(uart0), +}; + +static struct platform_device *xilinx_pdevices[] __initdata = { + &uart_device0, +}; + +/** + * board_ep107_init - Board specific initialization for the Xilinx EP107 board. + * + **/ +static void __init board_ep107_init(void) +{ + xilinx_system_init(); + platform_add_devices(&xilinx_pdevices[0], ARRAY_SIZE(xilinx_pdevices)); +} + +MACHINE_START(XILINX_EP107, "Xilinx EP107") + .boot_params = PLAT_PHYS_OFFSET + 0x00000100, + .map_io = xilinx_map_io, + .init_irq = xilinx_irq_init, + .init_machine = board_ep107_init, + .timer = &xttcpss_sys_timer, +MACHINE_END diff --git a/arch/arm/mach-xilinx/common.c b/arch/arm/mach-xilinx/common.c new file mode 100644 index 0000000..83b549d --- /dev/null +++ b/arch/arm/mach-xilinx/common.c @@ -0,0 +1,114 @@ +/* arch/arm/mach-xilinx/common.c + * + * This file contains common code that is intended to be used across + * boards so that it's not replicated. + * + * Copyright (C) 2011 Xilinx + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/cpumask.h> +#include <linux/platform_device.h> +#include <linux/clk.h> + +#include <asm/mach/map.h> +#include <asm/page.h> +#include <asm/hardware/gic.h> +#include <asm/hardware/cache-l2x0.h> + +#include <mach/xilinx_soc.h> +#include <mach/clkdev.h> +#include "common.h" + +/* + * Clock function infrastructure. + */ +int clk_enable(struct clk *clk) +{ + return 0; +} + +void clk_disable(struct clk *clk) +{ +} + +unsigned long clk_get_rate(struct clk *clk) +{ + return clk->rate; +} + +/** + * system_init - System specific initialization, intended to be called from + * board specific initialization. + * + **/ +void __init xilinx_system_init(void) +{ +#ifdef CONFIG_CACHE_L2X0 + /* + * 64KB way size, 8-way associativity, parity disabled + */ + l2x0_init(PL310_L2CC_BASE, 0x02060000, 0xF0F0FFFF); +#endif +} + +/** + * irq_init - Interrupt controller initialization for the GIC. + * + **/ +void __init xilinx_irq_init(void) +{ + gic_init(0, 29, SCU_GIC_DIST_BASE, SCU_GIC_CPU_BASE); +} + +/* The minimum devices needed to be mapped before the VM system is up and + * running include the GIC, UART and Timer Counter. + */ + +static struct map_desc io_desc[] __initdata = { + { + .virtual = TTC0_VIRT, + .pfn = __phys_to_pfn(TTC0_PHYS), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = SCU_PERIPH_VIRT, + .pfn = __phys_to_pfn(SCU_PERIPH_PHYS), + .length = SZ_8K, + .type = MT_DEVICE, + }, { + .virtual = PL310_L2CC_VIRT, + .pfn = __phys_to_pfn(PL310_L2CC_PHYS), + .length = SZ_4K, + .type = MT_DEVICE, + }, + +#ifdef CONFIG_DEBUG_LL + { + .virtual = UART0_VIRT, + .pfn = __phys_to_pfn(UART0_PHYS), + .length = SZ_4K, + .type = MT_DEVICE, + }, +#endif + +}; + +/** + * map_io - Create memory mappings needed for early I/O. + * + **/ +void __init xilinx_map_io(void) +{ + iotable_init(io_desc, ARRAY_SIZE(io_desc)); +} diff --git a/arch/arm/mach-xilinx/common.h b/arch/arm/mach-xilinx/common.h new file mode 100644 index 0000000..71f4ebc --- /dev/null +++ b/arch/arm/mach-xilinx/common.h @@ -0,0 +1,30 @@ +/* arch/arm/mach-xilinx/common.h + * + * This file contains common function prototypes to avoid externs + * in the c files. + * + * Copyright (C) 2011 Xilinx + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MACH_XILINX_COMMON_H__ +#define __MACH_XILINX_COMMON_H__ + +#include <linux/init.h> +#include <asm/mach/time.h> + +void __init xilinx_system_init(void); +void __init xilinx_irq_init(void); +void __init xilinx_map_io(void); + +extern struct sys_timer xttcpss_sys_timer; + +#endif -- 1.6.2.1 This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately. ^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH V5 1/4] ARM: Xilinx: Adding Xilinx board support @ 2011-03-30 0:24 ` John Linn 0 siblings, 0 replies; 22+ messages in thread From: John Linn @ 2011-03-30 0:24 UTC (permalink / raw) To: linux-arm-kernel, linux-kernel, linux, catalin.marinas, glikely, jamie, arnd Cc: John Linn The 1st board support is minimal to get a system up and running on the Xilinx platform. Signed-off-by: John Linn <john.linn@xilinx.com> --- V5 Changes Minor cleanup based on input from Jamie Iles. Update to work with code in next merge (PLAT_PHYS_OFFSET). V4 Changes Minor cleanup based on input from Jamie Iles. V3 Changes Updates based on Russell Kings' comments Changed headers to update the license info and remove the address Changed the name of functions to include "xilinx" in common.c and common.h Changed the Kconfig and Makefile to use MACH_XILINX which matches the machine registered. V2 Changes Updates based on Russell King's comments minor cleanups cleaned up physical/virtual addresses in early i/o table arch/arm/mach-xilinx/Kconfig | 14 +++++ arch/arm/mach-xilinx/Makefile | 7 ++ arch/arm/mach-xilinx/Makefile.boot | 3 + arch/arm/mach-xilinx/board_ep107.c | 85 +++++++++++++++++++++++++++ arch/arm/mach-xilinx/common.c | 114 ++++++++++++++++++++++++++++++++++++ arch/arm/mach-xilinx/common.h | 30 +++++++++ 6 files changed, 253 insertions(+), 0 deletions(-) create mode 100644 arch/arm/mach-xilinx/Kconfig create mode 100644 arch/arm/mach-xilinx/Makefile create mode 100644 arch/arm/mach-xilinx/Makefile.boot create mode 100644 arch/arm/mach-xilinx/board_ep107.c create mode 100644 arch/arm/mach-xilinx/common.c create mode 100644 arch/arm/mach-xilinx/common.h diff --git a/arch/arm/mach-xilinx/Kconfig b/arch/arm/mach-xilinx/Kconfig new file mode 100644 index 0000000..01181d2 --- /dev/null +++ b/arch/arm/mach-xilinx/Kconfig @@ -0,0 +1,14 @@ +if ARCH_XILINX + +choice + prompt "Board Selection" + default MACH_XILINX_EP107 + +config MACH_XILINX_EP107 + bool "Xilinx EP107 Board" + help + Select if you are using a Xilinx EP107 board. + +endchoice + +endif diff --git a/arch/arm/mach-xilinx/Makefile b/arch/arm/mach-xilinx/Makefile new file mode 100644 index 0000000..19489e7 --- /dev/null +++ b/arch/arm/mach-xilinx/Makefile @@ -0,0 +1,7 @@ +# +# Makefile for the linux kernel. +# + +# Common support +obj-y := common.o +obj-$(CONFIG_MACH_XILINX_EP107) += board_ep107.o diff --git a/arch/arm/mach-xilinx/Makefile.boot b/arch/arm/mach-xilinx/Makefile.boot new file mode 100644 index 0000000..67039c3 --- /dev/null +++ b/arch/arm/mach-xilinx/Makefile.boot @@ -0,0 +1,3 @@ + zreladdr-y := 0x00008000 +params_phys-y := 0x00000100 +initrd_phys-y := 0x00800000 diff --git a/arch/arm/mach-xilinx/board_ep107.c b/arch/arm/mach-xilinx/board_ep107.c new file mode 100644 index 0000000..f6abe3f --- /dev/null +++ b/arch/arm/mach-xilinx/board_ep107.c @@ -0,0 +1,85 @@ +/* arch/arm/mach-xilinx/board_ep107.c + * + * This file contains code specific to the Xilinx EP107 board. + * + * Copyright (C) 2011 Xilinx + * + * based on /arch/arm/mach-realview/core.c + * + * Copyright (C) 1999 - 2003 ARM Limited + * Copyright (C) 2000 Deep Blue Solutions Ltd + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/platform_device.h> +#include <linux/clkdev.h> + +#include <asm/mach-types.h> +#include <asm/mach/arch.h> + +#include <mach/xilinx_soc.h> +#include <mach/irqs.h> +#include <mach/memory.h> +#include "common.h" + +/* + * Fixed clocks for now + */ + +static struct clk ref50_clk = { + .rate = 50000000, +}; + +/* Create all the platform devices for the board */ + +static struct resource uart0[] = { + { + .start = UART0_PHYS, + .end = UART0_PHYS + 0xFFF, + .flags = IORESOURCE_MEM, + }, { + .start = IRQ_UART0, + .end = IRQ_UART0, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device uart_device0 = { + .name = "xuartpss", + .id = 0, + .dev = { + .platform_data = &ref50_clk.rate, + }, + .resource = uart0, + .num_resources = ARRAY_SIZE(uart0), +}; + +static struct platform_device *xilinx_pdevices[] __initdata = { + &uart_device0, +}; + +/** + * board_ep107_init - Board specific initialization for the Xilinx EP107 board. + * + **/ +static void __init board_ep107_init(void) +{ + xilinx_system_init(); + platform_add_devices(&xilinx_pdevices[0], ARRAY_SIZE(xilinx_pdevices)); +} + +MACHINE_START(XILINX_EP107, "Xilinx EP107") + .boot_params = PLAT_PHYS_OFFSET + 0x00000100, + .map_io = xilinx_map_io, + .init_irq = xilinx_irq_init, + .init_machine = board_ep107_init, + .timer = &xttcpss_sys_timer, +MACHINE_END diff --git a/arch/arm/mach-xilinx/common.c b/arch/arm/mach-xilinx/common.c new file mode 100644 index 0000000..83b549d --- /dev/null +++ b/arch/arm/mach-xilinx/common.c @@ -0,0 +1,114 @@ +/* arch/arm/mach-xilinx/common.c + * + * This file contains common code that is intended to be used across + * boards so that it's not replicated. + * + * Copyright (C) 2011 Xilinx + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/cpumask.h> +#include <linux/platform_device.h> +#include <linux/clk.h> + +#include <asm/mach/map.h> +#include <asm/page.h> +#include <asm/hardware/gic.h> +#include <asm/hardware/cache-l2x0.h> + +#include <mach/xilinx_soc.h> +#include <mach/clkdev.h> +#include "common.h" + +/* + * Clock function infrastructure. + */ +int clk_enable(struct clk *clk) +{ + return 0; +} + +void clk_disable(struct clk *clk) +{ +} + +unsigned long clk_get_rate(struct clk *clk) +{ + return clk->rate; +} + +/** + * system_init - System specific initialization, intended to be called from + * board specific initialization. + * + **/ +void __init xilinx_system_init(void) +{ +#ifdef CONFIG_CACHE_L2X0 + /* + * 64KB way size, 8-way associativity, parity disabled + */ + l2x0_init(PL310_L2CC_BASE, 0x02060000, 0xF0F0FFFF); +#endif +} + +/** + * irq_init - Interrupt controller initialization for the GIC. + * + **/ +void __init xilinx_irq_init(void) +{ + gic_init(0, 29, SCU_GIC_DIST_BASE, SCU_GIC_CPU_BASE); +} + +/* The minimum devices needed to be mapped before the VM system is up and + * running include the GIC, UART and Timer Counter. + */ + +static struct map_desc io_desc[] __initdata = { + { + .virtual = TTC0_VIRT, + .pfn = __phys_to_pfn(TTC0_PHYS), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = SCU_PERIPH_VIRT, + .pfn = __phys_to_pfn(SCU_PERIPH_PHYS), + .length = SZ_8K, + .type = MT_DEVICE, + }, { + .virtual = PL310_L2CC_VIRT, + .pfn = __phys_to_pfn(PL310_L2CC_PHYS), + .length = SZ_4K, + .type = MT_DEVICE, + }, + +#ifdef CONFIG_DEBUG_LL + { + .virtual = UART0_VIRT, + .pfn = __phys_to_pfn(UART0_PHYS), + .length = SZ_4K, + .type = MT_DEVICE, + }, +#endif + +}; + +/** + * map_io - Create memory mappings needed for early I/O. + * + **/ +void __init xilinx_map_io(void) +{ + iotable_init(io_desc, ARRAY_SIZE(io_desc)); +} diff --git a/arch/arm/mach-xilinx/common.h b/arch/arm/mach-xilinx/common.h new file mode 100644 index 0000000..71f4ebc --- /dev/null +++ b/arch/arm/mach-xilinx/common.h @@ -0,0 +1,30 @@ +/* arch/arm/mach-xilinx/common.h + * + * This file contains common function prototypes to avoid externs + * in the c files. + * + * Copyright (C) 2011 Xilinx + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MACH_XILINX_COMMON_H__ +#define __MACH_XILINX_COMMON_H__ + +#include <linux/init.h> +#include <asm/mach/time.h> + +void __init xilinx_system_init(void); +void __init xilinx_irq_init(void); +void __init xilinx_map_io(void); + +extern struct sys_timer xttcpss_sys_timer; + +#endif -- 1.6.2.1 This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately. ^ permalink raw reply related [flat|nested] 22+ messages in thread
[parent not found: <1301444651-18008-2-git-send-email-john.linn@xilinx.com>]
* [PATCH V5 2/4] ARM: Xilinx: Adding timer support to the platform [not found] ` <1301444651-18008-2-git-send-email-john.linn@xilinx.com> @ 2011-03-30 0:24 ` John Linn [not found] ` <1301444651-18008-3-git-send-email-john.linn@xilinx.com> 1 sibling, 0 replies; 22+ messages in thread From: John Linn @ 2011-03-30 0:24 UTC (permalink / raw) To: linux-arm-kernel The timer driver supports the Xilinx PS Timer Counter IP. Signed-off-by: Kiran Sutariya <kiran.sutariya@einfochips.com> Signed-off-by: John Linn <john.linn@xilinx.com> --- V5 Changes Minor cleanup based on input from Jamie Iles for sparse. Removed CLOCK_TICK_RATE based on input from Arnd. V4 Changes Minor cleanup based on input from Jamie Iles. Got rid of unused mode. Removed un-needed initialization. Made interrupt handler setup unconditional. V3 Changes Updates based on Russell Kings' comments Changed headers to update the license info and remove the address V2 Changes The timer code was changed quite a bit based on review inputs. It got much smaller and cleaner I think. Updates based on Russell King's comments minor cleanups for documentation comments removed the name from the timer structure removed interrupt for clock source moved to using clock functions provided in the kernel for calculating shift/mult values removed PM code as generic handles it Updated based on Jamie Iles's comment cleaned up ENABLE_MASK which was confusing now using platform_add_devices() from platform code moved base_addr to void __iomem pointer removed stop of the event timer in one shot mode arch/arm/mach-xilinx/Makefile | 2 +- arch/arm/mach-xilinx/timer.c | 297 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 298 insertions(+), 1 deletions(-) create mode 100644 arch/arm/mach-xilinx/timer.c diff --git a/arch/arm/mach-xilinx/Makefile b/arch/arm/mach-xilinx/Makefile index 19489e7..62787ff 100644 --- a/arch/arm/mach-xilinx/Makefile +++ b/arch/arm/mach-xilinx/Makefile @@ -3,5 +3,5 @@ # # Common support -obj-y := common.o +obj-y := common.o timer.o obj-$(CONFIG_MACH_XILINX_EP107) += board_ep107.o diff --git a/arch/arm/mach-xilinx/timer.c b/arch/arm/mach-xilinx/timer.c new file mode 100644 index 0000000..b2a72f0 --- /dev/null +++ b/arch/arm/mach-xilinx/timer.c @@ -0,0 +1,297 @@ +/* arch/arm/mach-xilinx/timer.c + * + * This file contains driver for the Xilinx PS Timer Counter IP. + * + * Copyright (C) 2011 Xilinx + * + * based on arch/mips/kernel/time.c timer driver + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/interrupt.h> +#include <linux/irq.h> +#include <linux/types.h> +#include <linux/clocksource.h> +#include <linux/clockchips.h> +#include <linux/io.h> + +#include <asm/mach/time.h> +#include <mach/xilinx_soc.h> +#include "common.h" + +/* + * This driver configures the 2 16-bit count-up timers as follows: + * + * T1: Timer 1, clocksource for generic timekeeping + * T2: Timer 2, clockevent source for hrtimers + * T3: Timer 3, <unused> + * + * The input frequency to the timer module for emulation is 2.5MHz which is + * common to all the timer channels (T1, T2, and T3). With a pre-scaler of 32, + * the timers are clocked at 78.125KHz (12.8 us resolution). + * + * The input frequency to the timer module in silicon will be 200MHz. With the + * pre-scaler of 32, the timers are clocked at 6.25MHz (160ns resolution). + */ +#define XTTCPSS_CLOCKSOURCE 0 /* Timer 1 as a generic timekeeping */ +#define XTTCPSS_CLOCKEVENT 1 /* Timer 2 as a clock event */ + +#define XTTCPSS_TIMER_BASE TTC0_BASE +#define XTTCPCC_EVENT_TIMER_IRQ (IRQ_TIMERCOUNTER0 + 1) +/* + * Timer Register Offset Definitions of Timer 1, Increment base address by 4 + * and use same offsets for Timer 2 + */ +#define XTTCPSS_CLK_CNTRL_OFFSET 0x00 /* Clock Control Reg, RW */ +#define XTTCPSS_CNT_CNTRL_OFFSET 0x0C /* Counter Control Reg, RW */ +#define XTTCPSS_COUNT_VAL_OFFSET 0x18 /* Counter Value Reg, RO */ +#define XTTCPSS_INTR_VAL_OFFSET 0x24 /* Interval Count Reg, RW */ +#define XTTCPSS_MATCH_1_OFFSET 0x30 /* Match 1 Value Reg, RW */ +#define XTTCPSS_MATCH_2_OFFSET 0x3C /* Match 2 Value Reg, RW */ +#define XTTCPSS_MATCH_3_OFFSET 0x48 /* Match 3 Value Reg, RW */ +#define XTTCPSS_ISR_OFFSET 0x54 /* Interrupt Status Reg, RO */ +#define XTTCPSS_IER_OFFSET 0x60 /* Interrupt Enable Reg, RW */ + +#define XTTCPSS_CNT_CNTRL_DISABLE_MASK 0x1 + +/* Setup the timers to use pre-scaling */ + +#define TIMER_RATE (PERIPHERAL_CLOCK_RATE / 32) + +/** + * struct xttcpss_timer - This definition defines local timer structure + * + * @base_addr: Base address of timer + **/ +struct xttcpss_timer { + void __iomem *base_addr; +}; + +static struct xttcpss_timer timers[2]; +static struct clock_event_device xttcpss_clockevent; + +/** + * xttcpss_set_interval - Set the timer interval value + * + * @timer: Pointer to the timer instance + * @cycles: Timer interval ticks + **/ +static void xttcpss_set_interval(struct xttcpss_timer *timer, + unsigned long cycles) +{ + u32 ctrl_reg; + + /* Disable the counter, set the counter value and re-enable counter */ + ctrl_reg = __raw_readl(timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET); + ctrl_reg |= XTTCPSS_CNT_CNTRL_DISABLE_MASK; + __raw_writel(ctrl_reg, timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET); + + __raw_writel(cycles, timer->base_addr + XTTCPSS_INTR_VAL_OFFSET); + + /* Reset the counter (0x10) so that it starts from 0, one-shot + mode makes this needed for timing to be right. */ + ctrl_reg |= 0x10; + ctrl_reg &= ~XTTCPSS_CNT_CNTRL_DISABLE_MASK; + __raw_writel(ctrl_reg, timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET); +} + +/** + * xttcpss_clock_event_interrupt - Clock event timer interrupt handler + * + * @irq: IRQ number of the Timer + * @dev_id: void pointer to the xttcpss_timer instance + * + * returns: Always IRQ_HANDLED - success + **/ +static irqreturn_t xttcpss_clock_event_interrupt(int irq, void *dev_id) +{ + struct clock_event_device *evt = &xttcpss_clockevent; + struct xttcpss_timer *timer = dev_id; + + /* Acknowledge the interrupt and call event handler */ + __raw_writel(__raw_readl(timer->base_addr + XTTCPSS_ISR_OFFSET), + timer->base_addr + XTTCPSS_ISR_OFFSET); + + evt->event_handler(evt); + + return IRQ_HANDLED; +} + +static struct irqaction event_timer_irq = { + .name = "xttcpss clockevent", + .flags = IRQF_DISABLED | IRQF_TIMER, + .handler = xttcpss_clock_event_interrupt, +}; + +/** + * xttcpss_timer_hardware_init - Initialize the timer hardware + * + * Initialize the hardware to start the clock source, get the clock + * event timer ready to use, and hook up the interrupt. + **/ +static void __init xttcpss_timer_hardware_init(void) +{ + /* Setup the clock source counter to be an incrementing counter + * with no interrupt and it rolls over at 0xFFFF. Pre-scale + it by 32 also. Let it start running now. + */ + timers[XTTCPSS_CLOCKSOURCE].base_addr = XTTCPSS_TIMER_BASE; + + __raw_writel(0x0, timers[XTTCPSS_CLOCKSOURCE].base_addr + + XTTCPSS_IER_OFFSET); + __raw_writel(0x9, timers[XTTCPSS_CLOCKSOURCE].base_addr + + XTTCPSS_CLK_CNTRL_OFFSET); + __raw_writel(0x10, timers[XTTCPSS_CLOCKSOURCE].base_addr + + XTTCPSS_CNT_CNTRL_OFFSET); + + /* Setup the clock event timer to be an interval timer which + * is prescaled by 32 using the interval interrupt. Leave it + * disabled for now. + */ + + timers[XTTCPSS_CLOCKEVENT].base_addr = XTTCPSS_TIMER_BASE + 4; + + __raw_writel(0x23, timers[XTTCPSS_CLOCKEVENT].base_addr + + XTTCPSS_CNT_CNTRL_OFFSET); + __raw_writel(0x9, timers[XTTCPSS_CLOCKEVENT].base_addr + + XTTCPSS_CLK_CNTRL_OFFSET); + __raw_writel(0x1, timers[XTTCPSS_CLOCKEVENT].base_addr + + XTTCPSS_IER_OFFSET); + + /* Setup IRQ the clock event timer */ + event_timer_irq.dev_id = &timers[XTTCPSS_CLOCKEVENT]; + setup_irq(XTTCPCC_EVENT_TIMER_IRQ, &event_timer_irq); +} + +/** + * __raw_readl_cycles - Reads the timer counter register + * + * returns: Current timer counter register value + **/ +static cycle_t __raw_readl_cycles(struct clocksource *cs) +{ + struct xttcpss_timer *timer = &timers[XTTCPSS_CLOCKSOURCE]; + + return (cycle_t)__raw_readl(timer->base_addr + + XTTCPSS_COUNT_VAL_OFFSET); +} + + +/* + * Instantiate and initialize the clock source structure + */ +static struct clocksource clocksource_xttcpss = { + .name = "xttcpss_timer1", + .rating = 200, /* Reasonable clock source */ + .read = __raw_readl_cycles, + .mask = CLOCKSOURCE_MASK(16), + .flags = CLOCK_SOURCE_IS_CONTINUOUS, +}; + + +/** + * xttcpss_set_next_event - Sets the time interval for next event + * + * @cycles: Timer interval ticks + * @evt: Address of clock event instance + * + * returns: Always 0 - success + **/ +static int xttcpss_set_next_event(unsigned long cycles, + struct clock_event_device *evt) +{ + struct xttcpss_timer *timer = &timers[XTTCPSS_CLOCKEVENT]; + + xttcpss_set_interval(timer, cycles); + return 0; +} + +/** + * xttcpss_set_mode - Sets the mode of timer + * + * @mode: Mode to be set + * @evt: Address of clock event instance + **/ +static void xttcpss_set_mode(enum clock_event_mode mode, + struct clock_event_device *evt) +{ + struct xttcpss_timer *timer = &timers[XTTCPSS_CLOCKEVENT]; + u32 ctrl_reg; + + switch (mode) { + case CLOCK_EVT_MODE_PERIODIC: + xttcpss_set_interval(timer, TIMER_RATE / HZ); + break; + case CLOCK_EVT_MODE_ONESHOT: + case CLOCK_EVT_MODE_UNUSED: + case CLOCK_EVT_MODE_SHUTDOWN: + ctrl_reg = __raw_readl(timer->base_addr + + XTTCPSS_CNT_CNTRL_OFFSET); + ctrl_reg |= XTTCPSS_CNT_CNTRL_DISABLE_MASK; + __raw_writel(ctrl_reg, + timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET); + break; + case CLOCK_EVT_MODE_RESUME: + ctrl_reg = __raw_readl(timer->base_addr + + XTTCPSS_CNT_CNTRL_OFFSET); + ctrl_reg &= ~XTTCPSS_CNT_CNTRL_DISABLE_MASK; + __raw_writel(ctrl_reg, + timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET); + break; + } +} + +/* + * Instantiate and initialize the clock event structure + */ +static struct clock_event_device xttcpss_clockevent = { + .name = "xttcpss_timer2", + .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, + .set_next_event = xttcpss_set_next_event, + .set_mode = xttcpss_set_mode, + .rating = 200, +}; + +/** + * xttcpss_timer_init - Initialize the timer + * + * Initializes the timer hardware and register the clock source and clock event + * timers with Linux kernal timer framework + **/ +static void __init xttcpss_timer_init(void) +{ + xttcpss_timer_hardware_init(); + clocksource_register_hz(&clocksource_xttcpss, TIMER_RATE); + + /* Calculate the parameters to allow the clockevent to operate using + integer math + */ + clockevents_calc_mult_shift(&xttcpss_clockevent, TIMER_RATE, 4); + + xttcpss_clockevent.max_delta_ns = + clockevent_delta2ns(0xfffe, &xttcpss_clockevent); + xttcpss_clockevent.min_delta_ns = + clockevent_delta2ns(1, &xttcpss_clockevent); + + /* Indicate that clock event can be used on any of the CPUs */ + + xttcpss_clockevent.cpumask = cpu_all_mask; + clockevents_register_device(&xttcpss_clockevent); +} + +/* + * Instantiate and initialize the system timer structure + */ +struct sys_timer xttcpss_sys_timer = { + .init = xttcpss_timer_init, +}; -- 1.6.2.1 This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. 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* [PATCH V5 2/4] ARM: Xilinx: Adding timer support to the platform @ 2011-03-30 0:24 ` John Linn 0 siblings, 0 replies; 22+ messages in thread From: John Linn @ 2011-03-30 0:24 UTC (permalink / raw) To: linux-arm-kernel, linux-kernel, linux, catalin.marinas, glikely, jamie, arnd Cc: John Linn, Kiran Sutariya The timer driver supports the Xilinx PS Timer Counter IP. Signed-off-by: Kiran Sutariya <kiran.sutariya@einfochips.com> Signed-off-by: John Linn <john.linn@xilinx.com> --- V5 Changes Minor cleanup based on input from Jamie Iles for sparse. Removed CLOCK_TICK_RATE based on input from Arnd. V4 Changes Minor cleanup based on input from Jamie Iles. Got rid of unused mode. Removed un-needed initialization. Made interrupt handler setup unconditional. V3 Changes Updates based on Russell Kings' comments Changed headers to update the license info and remove the address V2 Changes The timer code was changed quite a bit based on review inputs. It got much smaller and cleaner I think. Updates based on Russell King's comments minor cleanups for documentation comments removed the name from the timer structure removed interrupt for clock source moved to using clock functions provided in the kernel for calculating shift/mult values removed PM code as generic handles it Updated based on Jamie Iles's comment cleaned up ENABLE_MASK which was confusing now using platform_add_devices() from platform code moved base_addr to void __iomem pointer removed stop of the event timer in one shot mode arch/arm/mach-xilinx/Makefile | 2 +- arch/arm/mach-xilinx/timer.c | 297 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 298 insertions(+), 1 deletions(-) create mode 100644 arch/arm/mach-xilinx/timer.c diff --git a/arch/arm/mach-xilinx/Makefile b/arch/arm/mach-xilinx/Makefile index 19489e7..62787ff 100644 --- a/arch/arm/mach-xilinx/Makefile +++ b/arch/arm/mach-xilinx/Makefile @@ -3,5 +3,5 @@ # # Common support -obj-y := common.o +obj-y := common.o timer.o obj-$(CONFIG_MACH_XILINX_EP107) += board_ep107.o diff --git a/arch/arm/mach-xilinx/timer.c b/arch/arm/mach-xilinx/timer.c new file mode 100644 index 0000000..b2a72f0 --- /dev/null +++ b/arch/arm/mach-xilinx/timer.c @@ -0,0 +1,297 @@ +/* arch/arm/mach-xilinx/timer.c + * + * This file contains driver for the Xilinx PS Timer Counter IP. + * + * Copyright (C) 2011 Xilinx + * + * based on arch/mips/kernel/time.c timer driver + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/interrupt.h> +#include <linux/irq.h> +#include <linux/types.h> +#include <linux/clocksource.h> +#include <linux/clockchips.h> +#include <linux/io.h> + +#include <asm/mach/time.h> +#include <mach/xilinx_soc.h> +#include "common.h" + +/* + * This driver configures the 2 16-bit count-up timers as follows: + * + * T1: Timer 1, clocksource for generic timekeeping + * T2: Timer 2, clockevent source for hrtimers + * T3: Timer 3, <unused> + * + * The input frequency to the timer module for emulation is 2.5MHz which is + * common to all the timer channels (T1, T2, and T3). With a pre-scaler of 32, + * the timers are clocked at 78.125KHz (12.8 us resolution). + * + * The input frequency to the timer module in silicon will be 200MHz. With the + * pre-scaler of 32, the timers are clocked at 6.25MHz (160ns resolution). + */ +#define XTTCPSS_CLOCKSOURCE 0 /* Timer 1 as a generic timekeeping */ +#define XTTCPSS_CLOCKEVENT 1 /* Timer 2 as a clock event */ + +#define XTTCPSS_TIMER_BASE TTC0_BASE +#define XTTCPCC_EVENT_TIMER_IRQ (IRQ_TIMERCOUNTER0 + 1) +/* + * Timer Register Offset Definitions of Timer 1, Increment base address by 4 + * and use same offsets for Timer 2 + */ +#define XTTCPSS_CLK_CNTRL_OFFSET 0x00 /* Clock Control Reg, RW */ +#define XTTCPSS_CNT_CNTRL_OFFSET 0x0C /* Counter Control Reg, RW */ +#define XTTCPSS_COUNT_VAL_OFFSET 0x18 /* Counter Value Reg, RO */ +#define XTTCPSS_INTR_VAL_OFFSET 0x24 /* Interval Count Reg, RW */ +#define XTTCPSS_MATCH_1_OFFSET 0x30 /* Match 1 Value Reg, RW */ +#define XTTCPSS_MATCH_2_OFFSET 0x3C /* Match 2 Value Reg, RW */ +#define XTTCPSS_MATCH_3_OFFSET 0x48 /* Match 3 Value Reg, RW */ +#define XTTCPSS_ISR_OFFSET 0x54 /* Interrupt Status Reg, RO */ +#define XTTCPSS_IER_OFFSET 0x60 /* Interrupt Enable Reg, RW */ + +#define XTTCPSS_CNT_CNTRL_DISABLE_MASK 0x1 + +/* Setup the timers to use pre-scaling */ + +#define TIMER_RATE (PERIPHERAL_CLOCK_RATE / 32) + +/** + * struct xttcpss_timer - This definition defines local timer structure + * + * @base_addr: Base address of timer + **/ +struct xttcpss_timer { + void __iomem *base_addr; +}; + +static struct xttcpss_timer timers[2]; +static struct clock_event_device xttcpss_clockevent; + +/** + * xttcpss_set_interval - Set the timer interval value + * + * @timer: Pointer to the timer instance + * @cycles: Timer interval ticks + **/ +static void xttcpss_set_interval(struct xttcpss_timer *timer, + unsigned long cycles) +{ + u32 ctrl_reg; + + /* Disable the counter, set the counter value and re-enable counter */ + ctrl_reg = __raw_readl(timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET); + ctrl_reg |= XTTCPSS_CNT_CNTRL_DISABLE_MASK; + __raw_writel(ctrl_reg, timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET); + + __raw_writel(cycles, timer->base_addr + XTTCPSS_INTR_VAL_OFFSET); + + /* Reset the counter (0x10) so that it starts from 0, one-shot + mode makes this needed for timing to be right. */ + ctrl_reg |= 0x10; + ctrl_reg &= ~XTTCPSS_CNT_CNTRL_DISABLE_MASK; + __raw_writel(ctrl_reg, timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET); +} + +/** + * xttcpss_clock_event_interrupt - Clock event timer interrupt handler + * + * @irq: IRQ number of the Timer + * @dev_id: void pointer to the xttcpss_timer instance + * + * returns: Always IRQ_HANDLED - success + **/ +static irqreturn_t xttcpss_clock_event_interrupt(int irq, void *dev_id) +{ + struct clock_event_device *evt = &xttcpss_clockevent; + struct xttcpss_timer *timer = dev_id; + + /* Acknowledge the interrupt and call event handler */ + __raw_writel(__raw_readl(timer->base_addr + XTTCPSS_ISR_OFFSET), + timer->base_addr + XTTCPSS_ISR_OFFSET); + + evt->event_handler(evt); + + return IRQ_HANDLED; +} + +static struct irqaction event_timer_irq = { + .name = "xttcpss clockevent", + .flags = IRQF_DISABLED | IRQF_TIMER, + .handler = xttcpss_clock_event_interrupt, +}; + +/** + * xttcpss_timer_hardware_init - Initialize the timer hardware + * + * Initialize the hardware to start the clock source, get the clock + * event timer ready to use, and hook up the interrupt. + **/ +static void __init xttcpss_timer_hardware_init(void) +{ + /* Setup the clock source counter to be an incrementing counter + * with no interrupt and it rolls over at 0xFFFF. Pre-scale + it by 32 also. Let it start running now. + */ + timers[XTTCPSS_CLOCKSOURCE].base_addr = XTTCPSS_TIMER_BASE; + + __raw_writel(0x0, timers[XTTCPSS_CLOCKSOURCE].base_addr + + XTTCPSS_IER_OFFSET); + __raw_writel(0x9, timers[XTTCPSS_CLOCKSOURCE].base_addr + + XTTCPSS_CLK_CNTRL_OFFSET); + __raw_writel(0x10, timers[XTTCPSS_CLOCKSOURCE].base_addr + + XTTCPSS_CNT_CNTRL_OFFSET); + + /* Setup the clock event timer to be an interval timer which + * is prescaled by 32 using the interval interrupt. Leave it + * disabled for now. + */ + + timers[XTTCPSS_CLOCKEVENT].base_addr = XTTCPSS_TIMER_BASE + 4; + + __raw_writel(0x23, timers[XTTCPSS_CLOCKEVENT].base_addr + + XTTCPSS_CNT_CNTRL_OFFSET); + __raw_writel(0x9, timers[XTTCPSS_CLOCKEVENT].base_addr + + XTTCPSS_CLK_CNTRL_OFFSET); + __raw_writel(0x1, timers[XTTCPSS_CLOCKEVENT].base_addr + + XTTCPSS_IER_OFFSET); + + /* Setup IRQ the clock event timer */ + event_timer_irq.dev_id = &timers[XTTCPSS_CLOCKEVENT]; + setup_irq(XTTCPCC_EVENT_TIMER_IRQ, &event_timer_irq); +} + +/** + * __raw_readl_cycles - Reads the timer counter register + * + * returns: Current timer counter register value + **/ +static cycle_t __raw_readl_cycles(struct clocksource *cs) +{ + struct xttcpss_timer *timer = &timers[XTTCPSS_CLOCKSOURCE]; + + return (cycle_t)__raw_readl(timer->base_addr + + XTTCPSS_COUNT_VAL_OFFSET); +} + + +/* + * Instantiate and initialize the clock source structure + */ +static struct clocksource clocksource_xttcpss = { + .name = "xttcpss_timer1", + .rating = 200, /* Reasonable clock source */ + .read = __raw_readl_cycles, + .mask = CLOCKSOURCE_MASK(16), + .flags = CLOCK_SOURCE_IS_CONTINUOUS, +}; + + +/** + * xttcpss_set_next_event - Sets the time interval for next event + * + * @cycles: Timer interval ticks + * @evt: Address of clock event instance + * + * returns: Always 0 - success + **/ +static int xttcpss_set_next_event(unsigned long cycles, + struct clock_event_device *evt) +{ + struct xttcpss_timer *timer = &timers[XTTCPSS_CLOCKEVENT]; + + xttcpss_set_interval(timer, cycles); + return 0; +} + +/** + * xttcpss_set_mode - Sets the mode of timer + * + * @mode: Mode to be set + * @evt: Address of clock event instance + **/ +static void xttcpss_set_mode(enum clock_event_mode mode, + struct clock_event_device *evt) +{ + struct xttcpss_timer *timer = &timers[XTTCPSS_CLOCKEVENT]; + u32 ctrl_reg; + + switch (mode) { + case CLOCK_EVT_MODE_PERIODIC: + xttcpss_set_interval(timer, TIMER_RATE / HZ); + break; + case CLOCK_EVT_MODE_ONESHOT: + case CLOCK_EVT_MODE_UNUSED: + case CLOCK_EVT_MODE_SHUTDOWN: + ctrl_reg = __raw_readl(timer->base_addr + + XTTCPSS_CNT_CNTRL_OFFSET); + ctrl_reg |= XTTCPSS_CNT_CNTRL_DISABLE_MASK; + __raw_writel(ctrl_reg, + timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET); + break; + case CLOCK_EVT_MODE_RESUME: + ctrl_reg = __raw_readl(timer->base_addr + + XTTCPSS_CNT_CNTRL_OFFSET); + ctrl_reg &= ~XTTCPSS_CNT_CNTRL_DISABLE_MASK; + __raw_writel(ctrl_reg, + timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET); + break; + } +} + +/* + * Instantiate and initialize the clock event structure + */ +static struct clock_event_device xttcpss_clockevent = { + .name = "xttcpss_timer2", + .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, + .set_next_event = xttcpss_set_next_event, + .set_mode = xttcpss_set_mode, + .rating = 200, +}; + +/** + * xttcpss_timer_init - Initialize the timer + * + * Initializes the timer hardware and register the clock source and clock event + * timers with Linux kernal timer framework + **/ +static void __init xttcpss_timer_init(void) +{ + xttcpss_timer_hardware_init(); + clocksource_register_hz(&clocksource_xttcpss, TIMER_RATE); + + /* Calculate the parameters to allow the clockevent to operate using + integer math + */ + clockevents_calc_mult_shift(&xttcpss_clockevent, TIMER_RATE, 4); + + xttcpss_clockevent.max_delta_ns = + clockevent_delta2ns(0xfffe, &xttcpss_clockevent); + xttcpss_clockevent.min_delta_ns = + clockevent_delta2ns(1, &xttcpss_clockevent); + + /* Indicate that clock event can be used on any of the CPUs */ + + xttcpss_clockevent.cpumask = cpu_all_mask; + clockevents_register_device(&xttcpss_clockevent); +} + +/* + * Instantiate and initialize the system timer structure + */ +struct sys_timer xttcpss_sys_timer = { + .init = xttcpss_timer_init, +}; -- 1.6.2.1 This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. 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[parent not found: <1301444651-18008-3-git-send-email-john.linn@xilinx.com>]
* [PATCH V5 3/4] ARM: Xilinx: base header files and assembly macros [not found] ` <1301444651-18008-3-git-send-email-john.linn@xilinx.com> @ 2011-03-30 0:24 ` John Linn [not found] ` <1301444651-18008-4-git-send-email-john.linn@xilinx.com> 1 sibling, 0 replies; 22+ messages in thread From: John Linn @ 2011-03-30 0:24 UTC (permalink / raw) To: linux-arm-kernel These are the minimum needed to build the kernel for the new platform. Signed-off-by: John Linn <john.linn@xilinx.com> --- V5 Changes Minor cleanup based on input from Russell King (uncompress.h.). Minor cleanup based on input from Jamie Iles (uncompress.h.). Moved to minimal dependencies on CLOCK_TICK_RATE based on input from Arnd. V4 Changes Cleanup based on input from Jamie Iles. Moved to PLAT_PHYS_OFFSET. Remove headers file inclusions that weren't needed. Added use of raw_readl/raw_writel in uncompressor uart code. Added cpu_relax() in the uncompressor uart code. V3 Changes Updates based on Russell Kings' comments Changed headers to update the license info and remove the address Updated the constant to use UL in vmalloc.h V2 Changes Updates based on Russell King's comments moved to using entry-macro-gic.S moved stuff from hardware.h to xilinx_soc.h added IOMEM() in io.h to help with typing Minor updates to IO_SPACE_LIMIT and __io() Updated addresses to be clear with seperate virtual and physical addresses arch/arm/mach-xilinx/include/mach/clkdev.h | 33 +++++++++++++++ arch/arm/mach-xilinx/include/mach/debug-macro.S | 36 ++++++++++++++++ arch/arm/mach-xilinx/include/mach/entry-macro.S | 30 +++++++++++++ arch/arm/mach-xilinx/include/mach/hardware.h | 18 ++++++++ arch/arm/mach-xilinx/include/mach/io.h | 33 +++++++++++++++ arch/arm/mach-xilinx/include/mach/irqs.h | 29 +++++++++++++ arch/arm/mach-xilinx/include/mach/memory.h | 23 ++++++++++ arch/arm/mach-xilinx/include/mach/system.h | 28 ++++++++++++ arch/arm/mach-xilinx/include/mach/timex.h | 23 ++++++++++ arch/arm/mach-xilinx/include/mach/uart.h | 25 +++++++++++ arch/arm/mach-xilinx/include/mach/uncompress.h | 51 +++++++++++++++++++++++ arch/arm/mach-xilinx/include/mach/vmalloc.h | 20 +++++++++ arch/arm/mach-xilinx/include/mach/xilinx_soc.h | 48 +++++++++++++++++++++ 13 files changed, 397 insertions(+), 0 deletions(-) create mode 100644 arch/arm/mach-xilinx/include/mach/clkdev.h create mode 100644 arch/arm/mach-xilinx/include/mach/debug-macro.S create mode 100644 arch/arm/mach-xilinx/include/mach/entry-macro.S create mode 100644 arch/arm/mach-xilinx/include/mach/hardware.h create mode 100644 arch/arm/mach-xilinx/include/mach/io.h create mode 100644 arch/arm/mach-xilinx/include/mach/irqs.h create mode 100644 arch/arm/mach-xilinx/include/mach/memory.h create mode 100644 arch/arm/mach-xilinx/include/mach/system.h create mode 100644 arch/arm/mach-xilinx/include/mach/timex.h create mode 100644 arch/arm/mach-xilinx/include/mach/uart.h create mode 100644 arch/arm/mach-xilinx/include/mach/uncompress.h create mode 100644 arch/arm/mach-xilinx/include/mach/vmalloc.h create mode 100644 arch/arm/mach-xilinx/include/mach/xilinx_soc.h diff --git a/arch/arm/mach-xilinx/include/mach/clkdev.h b/arch/arm/mach-xilinx/include/mach/clkdev.h new file mode 100644 index 0000000..5dd1453 --- /dev/null +++ b/arch/arm/mach-xilinx/include/mach/clkdev.h @@ -0,0 +1,33 @@ +/* + * arch/arm/mach-xilinx/include/mach/clkdev.h + * + * Copyright (C) 2011 Xilinx, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __MACH_CLKDEV_H__ +#define __MACH_CLKDEV_H__ + +struct clk { + unsigned long rate; +}; + +static inline int __clk_get(struct clk *clk) +{ + return 1; +} + +static inline void __clk_put(struct clk *clk) +{ +} + +#endif diff --git a/arch/arm/mach-xilinx/include/mach/debug-macro.S b/arch/arm/mach-xilinx/include/mach/debug-macro.S new file mode 100644 index 0000000..30d3d3d --- /dev/null +++ b/arch/arm/mach-xilinx/include/mach/debug-macro.S @@ -0,0 +1,36 @@ +/* arch/arm/mach-xilinx/include/mach/debug-macro.S + * + * Debugging macro include header + * + * Copyright (C) 2011 Xilinx + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <mach/xilinx_soc.h> +#include <mach/uart.h> + + .macro addruart, rp, rv + ldr \rp, =LL_UART_PADDR @ physical + ldr \rv, =LL_UART_VADDR @ virtual + .endm + + .macro senduart,rd,rx + str \rd, [\rx, #UART_FIFO_OFFSET] @ TXDATA + .endm + + .macro waituart,rd,rx + .endm + + .macro busyuart,rd,rx +1002: ldr \rd, [\rx, #UART_SR_OFFSET] @ get status register + tst \rd, #UART_SR_TXFULL @ + bne 1002b @ wait if FIFO is full + .endm diff --git a/arch/arm/mach-xilinx/include/mach/entry-macro.S b/arch/arm/mach-xilinx/include/mach/entry-macro.S new file mode 100644 index 0000000..11a2866 --- /dev/null +++ b/arch/arm/mach-xilinx/include/mach/entry-macro.S @@ -0,0 +1,30 @@ +/* + * arch/arm/mach-xilinx/include/mach/entry-macro.S + * + * Low-level IRQ helper macros + * + * Copyright (C) 2011 Xilinx + * + * based on arch/plat-mxc/include/mach/entry-macro.S + * + * Copyright (C) 2007 Lennert Buytenhek <buytenh@wantstofly.org> + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <mach/hardware.h> +#include <asm/hardware/entry-macro-gic.S> + + .macro disable_fiq + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + .endm diff --git a/arch/arm/mach-xilinx/include/mach/hardware.h b/arch/arm/mach-xilinx/include/mach/hardware.h new file mode 100644 index 0000000..f9685c4 --- /dev/null +++ b/arch/arm/mach-xilinx/include/mach/hardware.h @@ -0,0 +1,18 @@ +/* arch/arm/mach-xilinx/include/mach/hardware.h + * + * Copyright (C) 2011 Xilinx + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MACH_HARDWARE_H__ +#define __MACH_HARDWARE_H__ + +#endif diff --git a/arch/arm/mach-xilinx/include/mach/io.h b/arch/arm/mach-xilinx/include/mach/io.h new file mode 100644 index 0000000..ef69e65 --- /dev/null +++ b/arch/arm/mach-xilinx/include/mach/io.h @@ -0,0 +1,33 @@ +/* arch/arm/mach-xilinx/include/mach/io.h + * + * Copyright (C) 2011 Xilinx + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MACH_IO_H__ +#define __MACH_IO_H__ + +/* Allow IO space to be anywhere in the memory */ + +#define IO_SPACE_LIMIT 0xffff + +/* IO address mapping macros, nothing special at this time but required */ + +#ifdef __ASSEMBLER__ +#define IOMEM(x) (x) +#else +#define IOMEM(x) ((void __force __iomem *)(x)) +#endif + +#define __io(a) __typesafe_io(a) +#define __mem_pci(a) (a) + +#endif diff --git a/arch/arm/mach-xilinx/include/mach/irqs.h b/arch/arm/mach-xilinx/include/mach/irqs.h new file mode 100644 index 0000000..47a8162 --- /dev/null +++ b/arch/arm/mach-xilinx/include/mach/irqs.h @@ -0,0 +1,29 @@ +/* arch/arm/mach-xilinx/include/mach/irqs.h + * + * Copyright (C) 2011 Xilinx + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MACH_IRQS_H +#define __MACH_IRQS_H + +#define ARCH_NR_GPIOS 118 +#define NR_IRQS (128 + ARCH_NR_GPIOS) + +/* + * GIC Interrupts + */ + +#define IRQ_GIC_SPI_START 32 +#define IRQ_TIMERCOUNTER0 42 +#define IRQ_UART0 59 + +#endif diff --git a/arch/arm/mach-xilinx/include/mach/memory.h b/arch/arm/mach-xilinx/include/mach/memory.h new file mode 100644 index 0000000..b683b0e --- /dev/null +++ b/arch/arm/mach-xilinx/include/mach/memory.h @@ -0,0 +1,23 @@ +/* arch/arm/mach-xilinx/include/mach/memory.h + * + * Copyright (C) 2011 Xilinx + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MACH_MEMORY_H__ +#define __MACH_MEMORY_H__ + +#include <asm/sizes.h> + +#define PLAT_PHYS_OFFSET UL(0x0) +#define MEM_SIZE SZ_256M + +#endif diff --git a/arch/arm/mach-xilinx/include/mach/system.h b/arch/arm/mach-xilinx/include/mach/system.h new file mode 100644 index 0000000..e8514a0 --- /dev/null +++ b/arch/arm/mach-xilinx/include/mach/system.h @@ -0,0 +1,28 @@ +/* arch/arm/mach-xilinx/include/mach/system.h + * + * Copyright (C) 2011 Xilinx + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MACH_SYSTEM_H__ +#define __MACH_SYSTEM_H__ + +static inline void arch_idle(void) +{ + cpu_do_idle(); +} + +static inline void arch_reset(char mode, const char *cmd) +{ + /* Add architecture specific reset processing here */ +} + +#endif diff --git a/arch/arm/mach-xilinx/include/mach/timex.h b/arch/arm/mach-xilinx/include/mach/timex.h new file mode 100644 index 0000000..e82e653 --- /dev/null +++ b/arch/arm/mach-xilinx/include/mach/timex.h @@ -0,0 +1,23 @@ +/* arch/arm/mach-xilinx/include/mach/timex.h + * + * Copyright (C) 2011 Xilinx + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MACH_TIMEX_H__ +#define __MACH_TIMEX_H__ + +/* the following is needed for the system to build but will be removed + in the future, the value is not important but won't hurt +*/ +#define CLOCK_TICK_RATE (100 * HZ) + +#endif diff --git a/arch/arm/mach-xilinx/include/mach/uart.h b/arch/arm/mach-xilinx/include/mach/uart.h new file mode 100644 index 0000000..7fca361 --- /dev/null +++ b/arch/arm/mach-xilinx/include/mach/uart.h @@ -0,0 +1,25 @@ +/* arch/arm/mach-xilinx/include/mach/uart.h + * + * Copyright (C) 2011 Xilinx + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MACH_UART_H__ +#define __MACH_UART_H__ + +#define UART_CR_OFFSET 0x00 /* Control Register [8:0] */ +#define UART_SR_OFFSET 0x2C /* Channel Status [11:0] */ +#define UART_FIFO_OFFSET 0x30 /* FIFO [15:0] or [7:0] */ + +#define UART_SR_TXFULL 0x00000010 /* TX FIFO full */ +#define UART_SR_TXEMPTY 0x00000008 /* TX FIFO empty */ + +#endif diff --git a/arch/arm/mach-xilinx/include/mach/uncompress.h b/arch/arm/mach-xilinx/include/mach/uncompress.h new file mode 100644 index 0000000..ef7dd81 --- /dev/null +++ b/arch/arm/mach-xilinx/include/mach/uncompress.h @@ -0,0 +1,51 @@ +/* arch/arm/mach-xilinx/include/mach/uncompress.h + * + * Copyright (C) 2011 Xilinx + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MACH_UNCOMPRESS_H__ +#define __MACH_UNCOMPRESS_H__ + +#include <linux/io.h> +#include <asm/processor.h> +#include <mach/xilinx_soc.h> +#include <mach/uart.h> + +void arch_decomp_setup(void) +{ +} + +static inline void flush(void) +{ + /* + * Wait while the FIFO is not empty + */ + while (!(__raw_readl(IOMEM(LL_UART_PADDR + UART_SR_OFFSET)) & + UART_SR_TXEMPTY)) + cpu_relax(); +} + +#define arch_decomp_wdog() + +static void putc(char ch) +{ + /* + * Wait for room in the FIFO, then write the char into the FIFO + */ + while (__raw_readl(IOMEM(LL_UART_PADDR + UART_SR_OFFSET)) & + UART_SR_TXFULL) + cpu_relax(); + + __raw_writel(ch, IOMEM(LL_UART_PADDR + UART_FIFO_OFFSET)); +} + +#endif diff --git a/arch/arm/mach-xilinx/include/mach/vmalloc.h b/arch/arm/mach-xilinx/include/mach/vmalloc.h new file mode 100644 index 0000000..aba20a3 --- /dev/null +++ b/arch/arm/mach-xilinx/include/mach/vmalloc.h @@ -0,0 +1,20 @@ +/* arch/arm/mach-xilinx/include/mach/vmalloc.h + * + * Copyright (C) 2011 Xilinx + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MACH_VMALLOC_H__ +#define __MACH_VMALLOC_H__ + +#define VMALLOC_END 0xE0000000UL + +#endif diff --git a/arch/arm/mach-xilinx/include/mach/xilinx_soc.h b/arch/arm/mach-xilinx/include/mach/xilinx_soc.h new file mode 100644 index 0000000..d181c5c --- /dev/null +++ b/arch/arm/mach-xilinx/include/mach/xilinx_soc.h @@ -0,0 +1,48 @@ +/* arch/arm/mach-xilinx/include/mach/xilinx_soc.h + * + * Copyright (C) 2011 Xilinx + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MACH_XILINX_SOC_H__ +#define __MACH_XILINX_SOC_H__ + +#define PERIPHERAL_CLOCK_RATE 2500000 + +/* For now, all mappings are flat (physical = virtual) + */ +#define UART0_PHYS 0xE0000000 +#define UART0_VIRT UART0_PHYS + +#define TTC0_PHYS 0xF8001000 +#define TTC0_VIRT TTC0_PHYS + +#define PL310_L2CC_PHYS 0xF8F02000 +#define PL310_L2CC_VIRT PL310_L2CC_PHYS + +#define SCU_PERIPH_PHYS 0xF8F00000 +#define SCU_PERIPH_VIRT SCU_PERIPH_PHYS + +/* The following are intended for the devices that are mapped early */ + +#define TTC0_BASE IOMEM(TTC0_VIRT) +#define SCU_PERIPH_BASE IOMEM(SCU_PERIPH_VIRT) +#define SCU_GIC_CPU_BASE (SCU_PERIPH_BASE + 0x100) +#define SCU_GIC_DIST_BASE (SCU_PERIPH_BASE + 0x1000) +#define PL310_L2CC_BASE IOMEM(PL310_L2CC_VIRT) + +/* + * Mandatory for CONFIG_LL_DEBUG, UART is mapped virtual = physical + */ +#define LL_UART_PADDR UART0_PHYS +#define LL_UART_VADDR UART0_VIRT + +#endif -- 1.6.2.1 This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately. ^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH V5 3/4] ARM: Xilinx: base header files and assembly macros @ 2011-03-30 0:24 ` John Linn 0 siblings, 0 replies; 22+ messages in thread From: John Linn @ 2011-03-30 0:24 UTC (permalink / raw) To: linux-arm-kernel, linux-kernel, linux, catalin.marinas, glikely, jamie, arnd Cc: John Linn These are the minimum needed to build the kernel for the new platform. Signed-off-by: John Linn <john.linn@xilinx.com> --- V5 Changes Minor cleanup based on input from Russell King (uncompress.h.). Minor cleanup based on input from Jamie Iles (uncompress.h.). Moved to minimal dependencies on CLOCK_TICK_RATE based on input from Arnd. V4 Changes Cleanup based on input from Jamie Iles. Moved to PLAT_PHYS_OFFSET. Remove headers file inclusions that weren't needed. Added use of raw_readl/raw_writel in uncompressor uart code. Added cpu_relax() in the uncompressor uart code. V3 Changes Updates based on Russell Kings' comments Changed headers to update the license info and remove the address Updated the constant to use UL in vmalloc.h V2 Changes Updates based on Russell King's comments moved to using entry-macro-gic.S moved stuff from hardware.h to xilinx_soc.h added IOMEM() in io.h to help with typing Minor updates to IO_SPACE_LIMIT and __io() Updated addresses to be clear with seperate virtual and physical addresses arch/arm/mach-xilinx/include/mach/clkdev.h | 33 +++++++++++++++ arch/arm/mach-xilinx/include/mach/debug-macro.S | 36 ++++++++++++++++ arch/arm/mach-xilinx/include/mach/entry-macro.S | 30 +++++++++++++ arch/arm/mach-xilinx/include/mach/hardware.h | 18 ++++++++ arch/arm/mach-xilinx/include/mach/io.h | 33 +++++++++++++++ arch/arm/mach-xilinx/include/mach/irqs.h | 29 +++++++++++++ arch/arm/mach-xilinx/include/mach/memory.h | 23 ++++++++++ arch/arm/mach-xilinx/include/mach/system.h | 28 ++++++++++++ arch/arm/mach-xilinx/include/mach/timex.h | 23 ++++++++++ arch/arm/mach-xilinx/include/mach/uart.h | 25 +++++++++++ arch/arm/mach-xilinx/include/mach/uncompress.h | 51 +++++++++++++++++++++++ arch/arm/mach-xilinx/include/mach/vmalloc.h | 20 +++++++++ arch/arm/mach-xilinx/include/mach/xilinx_soc.h | 48 +++++++++++++++++++++ 13 files changed, 397 insertions(+), 0 deletions(-) create mode 100644 arch/arm/mach-xilinx/include/mach/clkdev.h create mode 100644 arch/arm/mach-xilinx/include/mach/debug-macro.S create mode 100644 arch/arm/mach-xilinx/include/mach/entry-macro.S create mode 100644 arch/arm/mach-xilinx/include/mach/hardware.h create mode 100644 arch/arm/mach-xilinx/include/mach/io.h create mode 100644 arch/arm/mach-xilinx/include/mach/irqs.h create mode 100644 arch/arm/mach-xilinx/include/mach/memory.h create mode 100644 arch/arm/mach-xilinx/include/mach/system.h create mode 100644 arch/arm/mach-xilinx/include/mach/timex.h create mode 100644 arch/arm/mach-xilinx/include/mach/uart.h create mode 100644 arch/arm/mach-xilinx/include/mach/uncompress.h create mode 100644 arch/arm/mach-xilinx/include/mach/vmalloc.h create mode 100644 arch/arm/mach-xilinx/include/mach/xilinx_soc.h diff --git a/arch/arm/mach-xilinx/include/mach/clkdev.h b/arch/arm/mach-xilinx/include/mach/clkdev.h new file mode 100644 index 0000000..5dd1453 --- /dev/null +++ b/arch/arm/mach-xilinx/include/mach/clkdev.h @@ -0,0 +1,33 @@ +/* + * arch/arm/mach-xilinx/include/mach/clkdev.h + * + * Copyright (C) 2011 Xilinx, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __MACH_CLKDEV_H__ +#define __MACH_CLKDEV_H__ + +struct clk { + unsigned long rate; +}; + +static inline int __clk_get(struct clk *clk) +{ + return 1; +} + +static inline void __clk_put(struct clk *clk) +{ +} + +#endif diff --git a/arch/arm/mach-xilinx/include/mach/debug-macro.S b/arch/arm/mach-xilinx/include/mach/debug-macro.S new file mode 100644 index 0000000..30d3d3d --- /dev/null +++ b/arch/arm/mach-xilinx/include/mach/debug-macro.S @@ -0,0 +1,36 @@ +/* arch/arm/mach-xilinx/include/mach/debug-macro.S + * + * Debugging macro include header + * + * Copyright (C) 2011 Xilinx + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <mach/xilinx_soc.h> +#include <mach/uart.h> + + .macro addruart, rp, rv + ldr \rp, =LL_UART_PADDR @ physical + ldr \rv, =LL_UART_VADDR @ virtual + .endm + + .macro senduart,rd,rx + str \rd, [\rx, #UART_FIFO_OFFSET] @ TXDATA + .endm + + .macro waituart,rd,rx + .endm + + .macro busyuart,rd,rx +1002: ldr \rd, [\rx, #UART_SR_OFFSET] @ get status register + tst \rd, #UART_SR_TXFULL @ + bne 1002b @ wait if FIFO is full + .endm diff --git a/arch/arm/mach-xilinx/include/mach/entry-macro.S b/arch/arm/mach-xilinx/include/mach/entry-macro.S new file mode 100644 index 0000000..11a2866 --- /dev/null +++ b/arch/arm/mach-xilinx/include/mach/entry-macro.S @@ -0,0 +1,30 @@ +/* + * arch/arm/mach-xilinx/include/mach/entry-macro.S + * + * Low-level IRQ helper macros + * + * Copyright (C) 2011 Xilinx + * + * based on arch/plat-mxc/include/mach/entry-macro.S + * + * Copyright (C) 2007 Lennert Buytenhek <buytenh@wantstofly.org> + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <mach/hardware.h> +#include <asm/hardware/entry-macro-gic.S> + + .macro disable_fiq + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + .endm diff --git a/arch/arm/mach-xilinx/include/mach/hardware.h b/arch/arm/mach-xilinx/include/mach/hardware.h new file mode 100644 index 0000000..f9685c4 --- /dev/null +++ b/arch/arm/mach-xilinx/include/mach/hardware.h @@ -0,0 +1,18 @@ +/* arch/arm/mach-xilinx/include/mach/hardware.h + * + * Copyright (C) 2011 Xilinx + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MACH_HARDWARE_H__ +#define __MACH_HARDWARE_H__ + +#endif diff --git a/arch/arm/mach-xilinx/include/mach/io.h b/arch/arm/mach-xilinx/include/mach/io.h new file mode 100644 index 0000000..ef69e65 --- /dev/null +++ b/arch/arm/mach-xilinx/include/mach/io.h @@ -0,0 +1,33 @@ +/* arch/arm/mach-xilinx/include/mach/io.h + * + * Copyright (C) 2011 Xilinx + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MACH_IO_H__ +#define __MACH_IO_H__ + +/* Allow IO space to be anywhere in the memory */ + +#define IO_SPACE_LIMIT 0xffff + +/* IO address mapping macros, nothing special at this time but required */ + +#ifdef __ASSEMBLER__ +#define IOMEM(x) (x) +#else +#define IOMEM(x) ((void __force __iomem *)(x)) +#endif + +#define __io(a) __typesafe_io(a) +#define __mem_pci(a) (a) + +#endif diff --git a/arch/arm/mach-xilinx/include/mach/irqs.h b/arch/arm/mach-xilinx/include/mach/irqs.h new file mode 100644 index 0000000..47a8162 --- /dev/null +++ b/arch/arm/mach-xilinx/include/mach/irqs.h @@ -0,0 +1,29 @@ +/* arch/arm/mach-xilinx/include/mach/irqs.h + * + * Copyright (C) 2011 Xilinx + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MACH_IRQS_H +#define __MACH_IRQS_H + +#define ARCH_NR_GPIOS 118 +#define NR_IRQS (128 + ARCH_NR_GPIOS) + +/* + * GIC Interrupts + */ + +#define IRQ_GIC_SPI_START 32 +#define IRQ_TIMERCOUNTER0 42 +#define IRQ_UART0 59 + +#endif diff --git a/arch/arm/mach-xilinx/include/mach/memory.h b/arch/arm/mach-xilinx/include/mach/memory.h new file mode 100644 index 0000000..b683b0e --- /dev/null +++ b/arch/arm/mach-xilinx/include/mach/memory.h @@ -0,0 +1,23 @@ +/* arch/arm/mach-xilinx/include/mach/memory.h + * + * Copyright (C) 2011 Xilinx + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MACH_MEMORY_H__ +#define __MACH_MEMORY_H__ + +#include <asm/sizes.h> + +#define PLAT_PHYS_OFFSET UL(0x0) +#define MEM_SIZE SZ_256M + +#endif diff --git a/arch/arm/mach-xilinx/include/mach/system.h b/arch/arm/mach-xilinx/include/mach/system.h new file mode 100644 index 0000000..e8514a0 --- /dev/null +++ b/arch/arm/mach-xilinx/include/mach/system.h @@ -0,0 +1,28 @@ +/* arch/arm/mach-xilinx/include/mach/system.h + * + * Copyright (C) 2011 Xilinx + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MACH_SYSTEM_H__ +#define __MACH_SYSTEM_H__ + +static inline void arch_idle(void) +{ + cpu_do_idle(); +} + +static inline void arch_reset(char mode, const char *cmd) +{ + /* Add architecture specific reset processing here */ +} + +#endif diff --git a/arch/arm/mach-xilinx/include/mach/timex.h b/arch/arm/mach-xilinx/include/mach/timex.h new file mode 100644 index 0000000..e82e653 --- /dev/null +++ b/arch/arm/mach-xilinx/include/mach/timex.h @@ -0,0 +1,23 @@ +/* arch/arm/mach-xilinx/include/mach/timex.h + * + * Copyright (C) 2011 Xilinx + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MACH_TIMEX_H__ +#define __MACH_TIMEX_H__ + +/* the following is needed for the system to build but will be removed + in the future, the value is not important but won't hurt +*/ +#define CLOCK_TICK_RATE (100 * HZ) + +#endif diff --git a/arch/arm/mach-xilinx/include/mach/uart.h b/arch/arm/mach-xilinx/include/mach/uart.h new file mode 100644 index 0000000..7fca361 --- /dev/null +++ b/arch/arm/mach-xilinx/include/mach/uart.h @@ -0,0 +1,25 @@ +/* arch/arm/mach-xilinx/include/mach/uart.h + * + * Copyright (C) 2011 Xilinx + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MACH_UART_H__ +#define __MACH_UART_H__ + +#define UART_CR_OFFSET 0x00 /* Control Register [8:0] */ +#define UART_SR_OFFSET 0x2C /* Channel Status [11:0] */ +#define UART_FIFO_OFFSET 0x30 /* FIFO [15:0] or [7:0] */ + +#define UART_SR_TXFULL 0x00000010 /* TX FIFO full */ +#define UART_SR_TXEMPTY 0x00000008 /* TX FIFO empty */ + +#endif diff --git a/arch/arm/mach-xilinx/include/mach/uncompress.h b/arch/arm/mach-xilinx/include/mach/uncompress.h new file mode 100644 index 0000000..ef7dd81 --- /dev/null +++ b/arch/arm/mach-xilinx/include/mach/uncompress.h @@ -0,0 +1,51 @@ +/* arch/arm/mach-xilinx/include/mach/uncompress.h + * + * Copyright (C) 2011 Xilinx + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MACH_UNCOMPRESS_H__ +#define __MACH_UNCOMPRESS_H__ + +#include <linux/io.h> +#include <asm/processor.h> +#include <mach/xilinx_soc.h> +#include <mach/uart.h> + +void arch_decomp_setup(void) +{ +} + +static inline void flush(void) +{ + /* + * Wait while the FIFO is not empty + */ + while (!(__raw_readl(IOMEM(LL_UART_PADDR + UART_SR_OFFSET)) & + UART_SR_TXEMPTY)) + cpu_relax(); +} + +#define arch_decomp_wdog() + +static void putc(char ch) +{ + /* + * Wait for room in the FIFO, then write the char into the FIFO + */ + while (__raw_readl(IOMEM(LL_UART_PADDR + UART_SR_OFFSET)) & + UART_SR_TXFULL) + cpu_relax(); + + __raw_writel(ch, IOMEM(LL_UART_PADDR + UART_FIFO_OFFSET)); +} + +#endif diff --git a/arch/arm/mach-xilinx/include/mach/vmalloc.h b/arch/arm/mach-xilinx/include/mach/vmalloc.h new file mode 100644 index 0000000..aba20a3 --- /dev/null +++ b/arch/arm/mach-xilinx/include/mach/vmalloc.h @@ -0,0 +1,20 @@ +/* arch/arm/mach-xilinx/include/mach/vmalloc.h + * + * Copyright (C) 2011 Xilinx + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MACH_VMALLOC_H__ +#define __MACH_VMALLOC_H__ + +#define VMALLOC_END 0xE0000000UL + +#endif diff --git a/arch/arm/mach-xilinx/include/mach/xilinx_soc.h b/arch/arm/mach-xilinx/include/mach/xilinx_soc.h new file mode 100644 index 0000000..d181c5c --- /dev/null +++ b/arch/arm/mach-xilinx/include/mach/xilinx_soc.h @@ -0,0 +1,48 @@ +/* arch/arm/mach-xilinx/include/mach/xilinx_soc.h + * + * Copyright (C) 2011 Xilinx + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MACH_XILINX_SOC_H__ +#define __MACH_XILINX_SOC_H__ + +#define PERIPHERAL_CLOCK_RATE 2500000 + +/* For now, all mappings are flat (physical = virtual) + */ +#define UART0_PHYS 0xE0000000 +#define UART0_VIRT UART0_PHYS + +#define TTC0_PHYS 0xF8001000 +#define TTC0_VIRT TTC0_PHYS + +#define PL310_L2CC_PHYS 0xF8F02000 +#define PL310_L2CC_VIRT PL310_L2CC_PHYS + +#define SCU_PERIPH_PHYS 0xF8F00000 +#define SCU_PERIPH_VIRT SCU_PERIPH_PHYS + +/* The following are intended for the devices that are mapped early */ + +#define TTC0_BASE IOMEM(TTC0_VIRT) +#define SCU_PERIPH_BASE IOMEM(SCU_PERIPH_VIRT) +#define SCU_GIC_CPU_BASE (SCU_PERIPH_BASE + 0x100) +#define SCU_GIC_DIST_BASE (SCU_PERIPH_BASE + 0x1000) +#define PL310_L2CC_BASE IOMEM(PL310_L2CC_VIRT) + +/* + * Mandatory for CONFIG_LL_DEBUG, UART is mapped virtual = physical + */ +#define LL_UART_PADDR UART0_PHYS +#define LL_UART_VADDR UART0_VIRT + +#endif -- 1.6.2.1 This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately. ^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH V5 3/4] ARM: Xilinx: base header files and assembly macros 2011-03-30 0:24 ` John Linn @ 2011-03-30 11:44 ` Arnd Bergmann -1 siblings, 0 replies; 22+ messages in thread From: Arnd Bergmann @ 2011-03-30 11:44 UTC (permalink / raw) To: linux-arm-kernel Hi John, I looked over the latest version of your patches, everything looks good to me, but I found one problem that you have probably copied from other platforms: On Wednesday 30 March 2011, John Linn wrote: > + > +/* Allow IO space to be anywhere in the memory */ > + > +#define IO_SPACE_LIMIT 0xffff > + > +/* IO address mapping macros, nothing special at this time but required */ > + > +#ifdef __ASSEMBLER__ > +#define IOMEM(x) (x) > +#else > +#define IOMEM(x) ((void __force __iomem *)(x)) > +#endif > + > +#define __io(a) __typesafe_io(a) > +#define __mem_pci(a) (a) The definition of __io() looks wrong, so any call to inb()/outb() will be a wild pointer access when you add PCI support. If you don't plan to support PCI in the future, there should be no problem. Arnd ^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH V5 3/4] ARM: Xilinx: base header files and assembly macros @ 2011-03-30 11:44 ` Arnd Bergmann 0 siblings, 0 replies; 22+ messages in thread From: Arnd Bergmann @ 2011-03-30 11:44 UTC (permalink / raw) To: John Linn Cc: linux-arm-kernel, linux-kernel, linux, catalin.marinas, glikely, jamie Hi John, I looked over the latest version of your patches, everything looks good to me, but I found one problem that you have probably copied from other platforms: On Wednesday 30 March 2011, John Linn wrote: > + > +/* Allow IO space to be anywhere in the memory */ > + > +#define IO_SPACE_LIMIT 0xffff > + > +/* IO address mapping macros, nothing special at this time but required */ > + > +#ifdef __ASSEMBLER__ > +#define IOMEM(x) (x) > +#else > +#define IOMEM(x) ((void __force __iomem *)(x)) > +#endif > + > +#define __io(a) __typesafe_io(a) > +#define __mem_pci(a) (a) The definition of __io() looks wrong, so any call to inb()/outb() will be a wild pointer access when you add PCI support. If you don't plan to support PCI in the future, there should be no problem. Arnd ^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH V5 3/4] ARM: Xilinx: base header files and assembly macros 2011-03-30 11:44 ` Arnd Bergmann @ 2011-03-30 13:17 ` John Linn -1 siblings, 0 replies; 22+ messages in thread From: John Linn @ 2011-03-30 13:17 UTC (permalink / raw) To: linux-arm-kernel > -----Original Message----- > From: Arnd Bergmann [mailto:arnd at arndb.de] > Sent: Wednesday, March 30, 2011 5:45 AM > To: John Linn > Cc: linux-arm-kernel at lists.infradead.org; linux-kernel at vger.kernel.org; > linux at arm.linux.org.uk; catalin.marinas at arm.com; glikely at secretlab.ca; > jamie at jamieiles.com > Subject: Re: [PATCH V5 3/4] ARM: Xilinx: base header files and assembly > macros > > Hi John, > > I looked over the latest version of your patches, everything looks > good to me, but I found one problem that you have probably copied > from other platforms: Hi Arnd, Thanks for taking the time to review again. Yep I did copy from others. > > On Wednesday 30 March 2011, John Linn wrote: > > + > > +/* Allow IO space to be anywhere in the memory */ > > + > > +#define IO_SPACE_LIMIT 0xffff > > + > > +/* IO address mapping macros, nothing special at this time but > required */ > > + > > +#ifdef __ASSEMBLER__ > > +#define IOMEM(x) (x) > > +#else > > +#define IOMEM(x) ((void __force __iomem *)(x)) > > +#endif > > + > > +#define __io(a) __typesafe_io(a) > > +#define __mem_pci(a) (a) > > The definition of __io() looks wrong, so any call to inb()/outb() > will be a wild pointer access when you add PCI support. Yes that makes sense. We don't have immediate plans for PCI and I was assuming when we add PCI we would need to change that. If you think I shouldn't put it off then I'll fix it now. My preference was to get the platform supported, then add more features. Thanks, John > > If you don't plan to support PCI in the future, there should > be no problem. > > Arnd This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately. ^ permalink raw reply [flat|nested] 22+ messages in thread
* RE: [PATCH V5 3/4] ARM: Xilinx: base header files and assembly macros @ 2011-03-30 13:17 ` John Linn 0 siblings, 0 replies; 22+ messages in thread From: John Linn @ 2011-03-30 13:17 UTC (permalink / raw) To: Arnd Bergmann Cc: linux-arm-kernel, linux-kernel, linux, catalin.marinas, glikely, jamie > -----Original Message----- > From: Arnd Bergmann [mailto:arnd@arndb.de] > Sent: Wednesday, March 30, 2011 5:45 AM > To: John Linn > Cc: linux-arm-kernel@lists.infradead.org; linux-kernel@vger.kernel.org; > linux@arm.linux.org.uk; catalin.marinas@arm.com; glikely@secretlab.ca; > jamie@jamieiles.com > Subject: Re: [PATCH V5 3/4] ARM: Xilinx: base header files and assembly > macros > > Hi John, > > I looked over the latest version of your patches, everything looks > good to me, but I found one problem that you have probably copied > from other platforms: Hi Arnd, Thanks for taking the time to review again. Yep I did copy from others. > > On Wednesday 30 March 2011, John Linn wrote: > > + > > +/* Allow IO space to be anywhere in the memory */ > > + > > +#define IO_SPACE_LIMIT 0xffff > > + > > +/* IO address mapping macros, nothing special at this time but > required */ > > + > > +#ifdef __ASSEMBLER__ > > +#define IOMEM(x) (x) > > +#else > > +#define IOMEM(x) ((void __force __iomem *)(x)) > > +#endif > > + > > +#define __io(a) __typesafe_io(a) > > +#define __mem_pci(a) (a) > > The definition of __io() looks wrong, so any call to inb()/outb() > will be a wild pointer access when you add PCI support. Yes that makes sense. We don't have immediate plans for PCI and I was assuming when we add PCI we would need to change that. If you think I shouldn't put it off then I'll fix it now. My preference was to get the platform supported, then add more features. Thanks, John > > If you don't plan to support PCI in the future, there should > be no problem. > > Arnd This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately. ^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH V5 3/4] ARM: Xilinx: base header files and assembly macros 2011-03-30 13:17 ` John Linn @ 2011-03-30 13:29 ` Arnd Bergmann -1 siblings, 0 replies; 22+ messages in thread From: Arnd Bergmann @ 2011-03-30 13:29 UTC (permalink / raw) To: linux-arm-kernel On Wednesday 30 March 2011, John Linn wrote: > Yes that makes sense. We don't have immediate plans for PCI and > I was assuming when we add PCI we would need to change that. > > If you think I shouldn't put it off then I'll fix it now. My > preference was to get the platform supported, then add more features. Getting it fixed properly depends a bit on the PCI implementation. I've been planning to clean up this part of the ARM architecture for some time and I can probably do it for one more platform when I get to it. My idea for the multiplatform kernel is to have a global I/O space window (maybe 1 MB) that is in the same location in the virtual address space all the time, so any platform that wants to support PCI with direct-mapped I/O space can simply map it in there at boot time. Arnd ^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH V5 3/4] ARM: Xilinx: base header files and assembly macros @ 2011-03-30 13:29 ` Arnd Bergmann 0 siblings, 0 replies; 22+ messages in thread From: Arnd Bergmann @ 2011-03-30 13:29 UTC (permalink / raw) To: John Linn Cc: linux-arm-kernel, linux-kernel, linux, catalin.marinas, glikely, jamie On Wednesday 30 March 2011, John Linn wrote: > Yes that makes sense. We don't have immediate plans for PCI and > I was assuming when we add PCI we would need to change that. > > If you think I shouldn't put it off then I'll fix it now. My > preference was to get the platform supported, then add more features. Getting it fixed properly depends a bit on the PCI implementation. I've been planning to clean up this part of the ARM architecture for some time and I can probably do it for one more platform when I get to it. My idea for the multiplatform kernel is to have a global I/O space window (maybe 1 MB) that is in the same location in the virtual address space all the time, so any platform that wants to support PCI with direct-mapped I/O space can simply map it in there at boot time. Arnd ^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH V5 3/4] ARM: Xilinx: base header files and assembly macros 2011-03-30 13:29 ` Arnd Bergmann @ 2011-03-30 13:37 ` John Linn -1 siblings, 0 replies; 22+ messages in thread From: John Linn @ 2011-03-30 13:37 UTC (permalink / raw) To: linux-arm-kernel > -----Original Message----- > From: Arnd Bergmann [mailto:arnd at arndb.de] > Sent: Wednesday, March 30, 2011 7:29 AM > To: John Linn > Cc: linux-arm-kernel at lists.infradead.org; linux-kernel at vger.kernel.org; > linux at arm.linux.org.uk; catalin.marinas at arm.com; glikely at secretlab.ca; > jamie at jamieiles.com > Subject: Re: [PATCH V5 3/4] ARM: Xilinx: base header files and assembly > macros > > On Wednesday 30 March 2011, John Linn wrote: > > Yes that makes sense. We don't have immediate plans for PCI and > > I was assuming when we add PCI we would need to change that. > > > > If you think I shouldn't put it off then I'll fix it now. My > > preference was to get the platform supported, then add more features. > > Getting it fixed properly depends a bit on the PCI implementation. > I've been planning to clean up this part of the ARM architecture > for some time and I can probably do it for one more platform when > I get to it. Sounds like it's fine to postpone it til we do PCI as I don't know all the details of the system yet. Soft logic in FPGAs is great :) > > My idea for the multiplatform kernel is to have a global I/O space > window (maybe 1 MB) that is in the same location in the virtual > address space all the time, so any platform that wants to support > PCI with direct-mapped I/O space can simply map it in there > at boot time. > Sounds like that will make it easier for everyone and more consistent. Thanks, John > Arnd This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately. ^ permalink raw reply [flat|nested] 22+ messages in thread
* RE: [PATCH V5 3/4] ARM: Xilinx: base header files and assembly macros @ 2011-03-30 13:37 ` John Linn 0 siblings, 0 replies; 22+ messages in thread From: John Linn @ 2011-03-30 13:37 UTC (permalink / raw) To: Arnd Bergmann Cc: linux-arm-kernel, linux-kernel, linux, catalin.marinas, glikely, jamie > -----Original Message----- > From: Arnd Bergmann [mailto:arnd@arndb.de] > Sent: Wednesday, March 30, 2011 7:29 AM > To: John Linn > Cc: linux-arm-kernel@lists.infradead.org; linux-kernel@vger.kernel.org; > linux@arm.linux.org.uk; catalin.marinas@arm.com; glikely@secretlab.ca; > jamie@jamieiles.com > Subject: Re: [PATCH V5 3/4] ARM: Xilinx: base header files and assembly > macros > > On Wednesday 30 March 2011, John Linn wrote: > > Yes that makes sense. We don't have immediate plans for PCI and > > I was assuming when we add PCI we would need to change that. > > > > If you think I shouldn't put it off then I'll fix it now. My > > preference was to get the platform supported, then add more features. > > Getting it fixed properly depends a bit on the PCI implementation. > I've been planning to clean up this part of the ARM architecture > for some time and I can probably do it for one more platform when > I get to it. Sounds like it's fine to postpone it til we do PCI as I don't know all the details of the system yet. Soft logic in FPGAs is great :) > > My idea for the multiplatform kernel is to have a global I/O space > window (maybe 1 MB) that is in the same location in the virtual > address space all the time, so any platform that wants to support > PCI with direct-mapped I/O space can simply map it in there > at boot time. > Sounds like that will make it easier for everyone and more consistent. Thanks, John > Arnd This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately. ^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH V5 3/4] ARM: Xilinx: base header files and assembly macros 2011-03-30 13:29 ` Arnd Bergmann @ 2011-03-30 19:15 ` Russell King - ARM Linux -1 siblings, 0 replies; 22+ messages in thread From: Russell King - ARM Linux @ 2011-03-30 19:15 UTC (permalink / raw) To: linux-arm-kernel On Wed, Mar 30, 2011 at 03:29:03PM +0200, Arnd Bergmann wrote: > On Wednesday 30 March 2011, John Linn wrote: > > Yes that makes sense. We don't have immediate plans for PCI and > > I was assuming when we add PCI we would need to change that. > > > > If you think I shouldn't put it off then I'll fix it now. My > > preference was to get the platform supported, then add more features. > > Getting it fixed properly depends a bit on the PCI implementation. > I've been planning to clean up this part of the ARM architecture > for some time and I can probably do it for one more platform when > I get to it. > > My idea for the multiplatform kernel is to have a global I/O space > window (maybe 1 MB) that is in the same location in the virtual > address space all the time, so any platform that wants to support > PCI with direct-mapped I/O space can simply map it in there > at boot time. And how do you deal with PCMCIA implementations where each socket has its own separate IO space, each maybe several MB large and may be spread across several MB of memory with the PCMCIA attribute and PCMCIA memory spaces interspersed. Remember that PCMCIA drivers assume PCI/ISA IO support. What about platforms which have a real ISA IO space in addition to the PCMCIA IO spaces? Things aren't as simple as you'd like them to be, and sometimes changing this stuff changes userland too (think PCMCIA needing the IO regions declared to it from userspace during boot.) ^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH V5 3/4] ARM: Xilinx: base header files and assembly macros @ 2011-03-30 19:15 ` Russell King - ARM Linux 0 siblings, 0 replies; 22+ messages in thread From: Russell King - ARM Linux @ 2011-03-30 19:15 UTC (permalink / raw) To: Arnd Bergmann Cc: John Linn, linux-arm-kernel, linux-kernel, catalin.marinas, glikely, jamie On Wed, Mar 30, 2011 at 03:29:03PM +0200, Arnd Bergmann wrote: > On Wednesday 30 March 2011, John Linn wrote: > > Yes that makes sense. We don't have immediate plans for PCI and > > I was assuming when we add PCI we would need to change that. > > > > If you think I shouldn't put it off then I'll fix it now. My > > preference was to get the platform supported, then add more features. > > Getting it fixed properly depends a bit on the PCI implementation. > I've been planning to clean up this part of the ARM architecture > for some time and I can probably do it for one more platform when > I get to it. > > My idea for the multiplatform kernel is to have a global I/O space > window (maybe 1 MB) that is in the same location in the virtual > address space all the time, so any platform that wants to support > PCI with direct-mapped I/O space can simply map it in there > at boot time. And how do you deal with PCMCIA implementations where each socket has its own separate IO space, each maybe several MB large and may be spread across several MB of memory with the PCMCIA attribute and PCMCIA memory spaces interspersed. Remember that PCMCIA drivers assume PCI/ISA IO support. What about platforms which have a real ISA IO space in addition to the PCMCIA IO spaces? Things aren't as simple as you'd like them to be, and sometimes changing this stuff changes userland too (think PCMCIA needing the IO regions declared to it from userspace during boot.) ^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH V5 3/4] ARM: Xilinx: base header files and assembly macros 2011-03-30 19:15 ` Russell King - ARM Linux @ 2011-03-30 19:43 ` Arnd Bergmann -1 siblings, 0 replies; 22+ messages in thread From: Arnd Bergmann @ 2011-03-30 19:43 UTC (permalink / raw) To: linux-arm-kernel On Wednesday 30 March 2011 21:15:06 Russell King - ARM Linux wrote: > And how do you deal with PCMCIA implementations where each socket has > its own separate IO space, each maybe several MB large and may be spread > across several MB of memory with the PCMCIA attribute and PCMCIA memory > spaces interspersed. Remember that PCMCIA drivers assume PCI/ISA IO > support. I would assume that the majority of implementations uses regular (64KB) I/O spaces per bus, so within 1 MB, that could fit 16 of them. > What about platforms which have a real ISA IO space in addition to the > PCMCIA IO spaces? I'd do the same as on powerpc: One of them gets registered as the "primary" bus, which gets the first 64KB. This one is typically the only one that can support legacy ISA devices with hardcoded I/O port numbers. Any other bus (PCI, PCMCIA, secondary ISA if needed) can go into one of the other 15 64KB slots. > Things aren't as simple as you'd like them to be, and sometimes changing > this stuff changes userland too (think PCMCIA needing the IO regions > declared to it from userspace during boot.) Can you give an example what hardware or driver needs this? Anyway, the idea is more to have a standard implementation that can be used by most platforms without causing pain, getting us one step closer to a multiplatform kernel. If one of the more obscure platforms doesn't fit, it can still use its own variant and not be part of the multiplatform configuration. There are a lot of other things needed before we get there anyway. Arnd ^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH V5 3/4] ARM: Xilinx: base header files and assembly macros @ 2011-03-30 19:43 ` Arnd Bergmann 0 siblings, 0 replies; 22+ messages in thread From: Arnd Bergmann @ 2011-03-30 19:43 UTC (permalink / raw) To: linux-arm-kernel Cc: Russell King - ARM Linux, glikely, catalin.marinas, linux-kernel, jamie, John Linn On Wednesday 30 March 2011 21:15:06 Russell King - ARM Linux wrote: > And how do you deal with PCMCIA implementations where each socket has > its own separate IO space, each maybe several MB large and may be spread > across several MB of memory with the PCMCIA attribute and PCMCIA memory > spaces interspersed. Remember that PCMCIA drivers assume PCI/ISA IO > support. I would assume that the majority of implementations uses regular (64KB) I/O spaces per bus, so within 1 MB, that could fit 16 of them. > What about platforms which have a real ISA IO space in addition to the > PCMCIA IO spaces? I'd do the same as on powerpc: One of them gets registered as the "primary" bus, which gets the first 64KB. This one is typically the only one that can support legacy ISA devices with hardcoded I/O port numbers. Any other bus (PCI, PCMCIA, secondary ISA if needed) can go into one of the other 15 64KB slots. > Things aren't as simple as you'd like them to be, and sometimes changing > this stuff changes userland too (think PCMCIA needing the IO regions > declared to it from userspace during boot.) Can you give an example what hardware or driver needs this? Anyway, the idea is more to have a standard implementation that can be used by most platforms without causing pain, getting us one step closer to a multiplatform kernel. If one of the more obscure platforms doesn't fit, it can still use its own variant and not be part of the multiplatform configuration. There are a lot of other things needed before we get there anyway. Arnd ^ permalink raw reply [flat|nested] 22+ messages in thread
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* [PATCH V5 4/4] ARM: Xilinx: Adding Xilinx platform infrastructure support [not found] ` <1301444651-18008-4-git-send-email-john.linn@xilinx.com> @ 2011-03-30 0:24 ` John Linn 0 siblings, 0 replies; 22+ messages in thread From: John Linn @ 2011-03-30 0:24 UTC (permalink / raw) To: linux-arm-kernel Minimum infrastructure to add the Xilinx machine and allow it to be selected in the build. Signed-off-by: John Linn <john.linn@xilinx.com> --- No updates for V5 V4 Updated to apply against linux-next branch. No updates for V3 V2 Changes Updates based on Russell King's comments Cleanup of the Kconfig Moved this patch to be last in the patch series arch/arm/Kconfig | 13 +++++++++++++ arch/arm/Makefile | 1 + arch/arm/mm/Kconfig | 2 +- 3 files changed, 15 insertions(+), 1 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 5e15e6b..3983afa 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -891,6 +891,17 @@ config PLAT_SPEAR help Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx). +config ARCH_XILINX + bool "Xilinx ARM Cortex A9 Platform" + select CPU_V7 + select GENERIC_TIME + select GENERIC_CLOCKEVENTS + select CLKDEV_LOOKUP + select ARM_GIC + select ARM_AMBA + help + Support for Xilinx ARM Cortex A9 Platform + endchoice # @@ -1025,6 +1036,8 @@ source "arch/arm/mach-vexpress/Kconfig" source "arch/arm/mach-w90x900/Kconfig" +source "arch/arm/mach-xilinx/Kconfig" + # Definitions to make life easier config ARCH_ACORN bool diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 6f7b292..a78ecf2 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -197,6 +197,7 @@ machine-$(CONFIG_MACH_SPEAR300) := spear3xx machine-$(CONFIG_MACH_SPEAR310) := spear3xx machine-$(CONFIG_MACH_SPEAR320) := spear3xx machine-$(CONFIG_MACH_SPEAR600) := spear6xx +machine-$(CONFIG_ARCH_XILINX) := xilinx # Platform directory name. This list is sorted alphanumerically # by CONFIG_* macro name. diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index e4509ba..cb0c570 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -813,7 +813,7 @@ config CACHE_L2X0 depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \ REALVIEW_EB_A9MP || ARCH_MX35 || ARCH_MX31 || MACH_REALVIEW_PBX || \ ARCH_NOMADIK || ARCH_OMAP4 || ARCH_S5PV310 || ARCH_TEGRA || \ - ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || ARCH_SHMOBILE + ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || ARCH_SHMOBILE || ARCH_XILINX default y select OUTER_CACHE select OUTER_CACHE_SYNC -- 1.6.2.1 This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately. ^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH V5 4/4] ARM: Xilinx: Adding Xilinx platform infrastructure support @ 2011-03-30 0:24 ` John Linn 0 siblings, 0 replies; 22+ messages in thread From: John Linn @ 2011-03-30 0:24 UTC (permalink / raw) To: linux-arm-kernel, linux-kernel, linux, catalin.marinas, glikely, jamie, arnd Cc: John Linn Minimum infrastructure to add the Xilinx machine and allow it to be selected in the build. Signed-off-by: John Linn <john.linn@xilinx.com> --- No updates for V5 V4 Updated to apply against linux-next branch. No updates for V3 V2 Changes Updates based on Russell King's comments Cleanup of the Kconfig Moved this patch to be last in the patch series arch/arm/Kconfig | 13 +++++++++++++ arch/arm/Makefile | 1 + arch/arm/mm/Kconfig | 2 +- 3 files changed, 15 insertions(+), 1 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 5e15e6b..3983afa 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -891,6 +891,17 @@ config PLAT_SPEAR help Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx). +config ARCH_XILINX + bool "Xilinx ARM Cortex A9 Platform" + select CPU_V7 + select GENERIC_TIME + select GENERIC_CLOCKEVENTS + select CLKDEV_LOOKUP + select ARM_GIC + select ARM_AMBA + help + Support for Xilinx ARM Cortex A9 Platform + endchoice # @@ -1025,6 +1036,8 @@ source "arch/arm/mach-vexpress/Kconfig" source "arch/arm/mach-w90x900/Kconfig" +source "arch/arm/mach-xilinx/Kconfig" + # Definitions to make life easier config ARCH_ACORN bool diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 6f7b292..a78ecf2 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -197,6 +197,7 @@ machine-$(CONFIG_MACH_SPEAR300) := spear3xx machine-$(CONFIG_MACH_SPEAR310) := spear3xx machine-$(CONFIG_MACH_SPEAR320) := spear3xx machine-$(CONFIG_MACH_SPEAR600) := spear6xx +machine-$(CONFIG_ARCH_XILINX) := xilinx # Platform directory name. This list is sorted alphanumerically # by CONFIG_* macro name. diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index e4509ba..cb0c570 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -813,7 +813,7 @@ config CACHE_L2X0 depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \ REALVIEW_EB_A9MP || ARCH_MX35 || ARCH_MX31 || MACH_REALVIEW_PBX || \ ARCH_NOMADIK || ARCH_OMAP4 || ARCH_S5PV310 || ARCH_TEGRA || \ - ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || ARCH_SHMOBILE + ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || ARCH_SHMOBILE || ARCH_XILINX default y select OUTER_CACHE select OUTER_CACHE_SYNC -- 1.6.2.1 This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately. ^ permalink raw reply related [flat|nested] 22+ messages in thread
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* [PATCH V5 3/4] ARM: Xilinx: base header files and assembly macros [not found] ` <1298929919-510-3-git-send-email-john.linn@xilinx.com> @ 2011-02-28 21:51 ` John Linn 0 siblings, 0 replies; 22+ messages in thread From: John Linn @ 2011-02-28 21:51 UTC (permalink / raw) To: linux-arm-kernel These are the minimum needed to build the kernel for the new platform. Signed-off-by: John Linn <john.linn@xilinx.com> --- V5 Changes Minor cleanup based on input from Russell King (uncompress.h.). Minor cleanup based on input from Jamie Iles (uncompress.h.). Moved to minimal dependencies on CLOCK_TICK_RATE based on input from Arnd. V4 Changes Cleanup based on input from Jamie Iles. Moved to PLAT_PHYS_OFFSET. Remove headers file inclusions that weren't needed. Added use of raw_readl/raw_writel in uncompressor uart code. Added cpu_relax() in the uncompressor uart code. V3 Changes Updates based on Russell Kings' comments Changed headers to update the license info and remove the address Updated the constant to use UL in vmalloc.h V2 Changes Updates based on Russell King's comments moved to using entry-macro-gic.S moved stuff from hardware.h to xilinx_soc.h added IOMEM() in io.h to help with typing Minor updates to IO_SPACE_LIMIT and __io() Updated addresses to be clear with seperate virtual and physical addresses arch/arm/mach-xilinx/include/mach/clkdev.h | 33 +++++++++++++++ arch/arm/mach-xilinx/include/mach/debug-macro.S | 36 ++++++++++++++++ arch/arm/mach-xilinx/include/mach/entry-macro.S | 30 +++++++++++++ arch/arm/mach-xilinx/include/mach/hardware.h | 18 ++++++++ arch/arm/mach-xilinx/include/mach/io.h | 33 +++++++++++++++ arch/arm/mach-xilinx/include/mach/irqs.h | 29 +++++++++++++ arch/arm/mach-xilinx/include/mach/memory.h | 23 ++++++++++ arch/arm/mach-xilinx/include/mach/system.h | 28 ++++++++++++ arch/arm/mach-xilinx/include/mach/timex.h | 23 ++++++++++ arch/arm/mach-xilinx/include/mach/uart.h | 25 +++++++++++ arch/arm/mach-xilinx/include/mach/uncompress.h | 51 +++++++++++++++++++++++ arch/arm/mach-xilinx/include/mach/vmalloc.h | 20 +++++++++ arch/arm/mach-xilinx/include/mach/xilinx_soc.h | 48 +++++++++++++++++++++ 13 files changed, 397 insertions(+), 0 deletions(-) create mode 100644 arch/arm/mach-xilinx/include/mach/clkdev.h create mode 100644 arch/arm/mach-xilinx/include/mach/debug-macro.S create mode 100644 arch/arm/mach-xilinx/include/mach/entry-macro.S create mode 100644 arch/arm/mach-xilinx/include/mach/hardware.h create mode 100644 arch/arm/mach-xilinx/include/mach/io.h create mode 100644 arch/arm/mach-xilinx/include/mach/irqs.h create mode 100644 arch/arm/mach-xilinx/include/mach/memory.h create mode 100644 arch/arm/mach-xilinx/include/mach/system.h create mode 100644 arch/arm/mach-xilinx/include/mach/timex.h create mode 100644 arch/arm/mach-xilinx/include/mach/uart.h create mode 100644 arch/arm/mach-xilinx/include/mach/uncompress.h create mode 100644 arch/arm/mach-xilinx/include/mach/vmalloc.h create mode 100644 arch/arm/mach-xilinx/include/mach/xilinx_soc.h diff --git a/arch/arm/mach-xilinx/include/mach/clkdev.h b/arch/arm/mach-xilinx/include/mach/clkdev.h new file mode 100644 index 0000000..5dd1453 --- /dev/null +++ b/arch/arm/mach-xilinx/include/mach/clkdev.h @@ -0,0 +1,33 @@ +/* + * arch/arm/mach-xilinx/include/mach/clkdev.h + * + * Copyright (C) 2011 Xilinx, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __MACH_CLKDEV_H__ +#define __MACH_CLKDEV_H__ + +struct clk { + unsigned long rate; +}; + +static inline int __clk_get(struct clk *clk) +{ + return 1; +} + +static inline void __clk_put(struct clk *clk) +{ +} + +#endif diff --git a/arch/arm/mach-xilinx/include/mach/debug-macro.S b/arch/arm/mach-xilinx/include/mach/debug-macro.S new file mode 100644 index 0000000..30d3d3d --- /dev/null +++ b/arch/arm/mach-xilinx/include/mach/debug-macro.S @@ -0,0 +1,36 @@ +/* arch/arm/mach-xilinx/include/mach/debug-macro.S + * + * Debugging macro include header + * + * Copyright (C) 2011 Xilinx + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <mach/xilinx_soc.h> +#include <mach/uart.h> + + .macro addruart, rp, rv + ldr \rp, =LL_UART_PADDR @ physical + ldr \rv, =LL_UART_VADDR @ virtual + .endm + + .macro senduart,rd,rx + str \rd, [\rx, #UART_FIFO_OFFSET] @ TXDATA + .endm + + .macro waituart,rd,rx + .endm + + .macro busyuart,rd,rx +1002: ldr \rd, [\rx, #UART_SR_OFFSET] @ get status register + tst \rd, #UART_SR_TXFULL @ + bne 1002b @ wait if FIFO is full + .endm diff --git a/arch/arm/mach-xilinx/include/mach/entry-macro.S b/arch/arm/mach-xilinx/include/mach/entry-macro.S new file mode 100644 index 0000000..11a2866 --- /dev/null +++ b/arch/arm/mach-xilinx/include/mach/entry-macro.S @@ -0,0 +1,30 @@ +/* + * arch/arm/mach-xilinx/include/mach/entry-macro.S + * + * Low-level IRQ helper macros + * + * Copyright (C) 2011 Xilinx + * + * based on arch/plat-mxc/include/mach/entry-macro.S + * + * Copyright (C) 2007 Lennert Buytenhek <buytenh@wantstofly.org> + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <mach/hardware.h> +#include <asm/hardware/entry-macro-gic.S> + + .macro disable_fiq + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + .endm diff --git a/arch/arm/mach-xilinx/include/mach/hardware.h b/arch/arm/mach-xilinx/include/mach/hardware.h new file mode 100644 index 0000000..f9685c4 --- /dev/null +++ b/arch/arm/mach-xilinx/include/mach/hardware.h @@ -0,0 +1,18 @@ +/* arch/arm/mach-xilinx/include/mach/hardware.h + * + * Copyright (C) 2011 Xilinx + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MACH_HARDWARE_H__ +#define __MACH_HARDWARE_H__ + +#endif diff --git a/arch/arm/mach-xilinx/include/mach/io.h b/arch/arm/mach-xilinx/include/mach/io.h new file mode 100644 index 0000000..ef69e65 --- /dev/null +++ b/arch/arm/mach-xilinx/include/mach/io.h @@ -0,0 +1,33 @@ +/* arch/arm/mach-xilinx/include/mach/io.h + * + * Copyright (C) 2011 Xilinx + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MACH_IO_H__ +#define __MACH_IO_H__ + +/* Allow IO space to be anywhere in the memory */ + +#define IO_SPACE_LIMIT 0xffff + +/* IO address mapping macros, nothing special at this time but required */ + +#ifdef __ASSEMBLER__ +#define IOMEM(x) (x) +#else +#define IOMEM(x) ((void __force __iomem *)(x)) +#endif + +#define __io(a) __typesafe_io(a) +#define __mem_pci(a) (a) + +#endif diff --git a/arch/arm/mach-xilinx/include/mach/irqs.h b/arch/arm/mach-xilinx/include/mach/irqs.h new file mode 100644 index 0000000..47a8162 --- /dev/null +++ b/arch/arm/mach-xilinx/include/mach/irqs.h @@ -0,0 +1,29 @@ +/* arch/arm/mach-xilinx/include/mach/irqs.h + * + * Copyright (C) 2011 Xilinx + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MACH_IRQS_H +#define __MACH_IRQS_H + +#define ARCH_NR_GPIOS 118 +#define NR_IRQS (128 + ARCH_NR_GPIOS) + +/* + * GIC Interrupts + */ + +#define IRQ_GIC_SPI_START 32 +#define IRQ_TIMERCOUNTER0 42 +#define IRQ_UART0 59 + +#endif diff --git a/arch/arm/mach-xilinx/include/mach/memory.h b/arch/arm/mach-xilinx/include/mach/memory.h new file mode 100644 index 0000000..b683b0e --- /dev/null +++ b/arch/arm/mach-xilinx/include/mach/memory.h @@ -0,0 +1,23 @@ +/* arch/arm/mach-xilinx/include/mach/memory.h + * + * Copyright (C) 2011 Xilinx + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MACH_MEMORY_H__ +#define __MACH_MEMORY_H__ + +#include <asm/sizes.h> + +#define PLAT_PHYS_OFFSET UL(0x0) +#define MEM_SIZE SZ_256M + +#endif diff --git a/arch/arm/mach-xilinx/include/mach/system.h b/arch/arm/mach-xilinx/include/mach/system.h new file mode 100644 index 0000000..e8514a0 --- /dev/null +++ b/arch/arm/mach-xilinx/include/mach/system.h @@ -0,0 +1,28 @@ +/* arch/arm/mach-xilinx/include/mach/system.h + * + * Copyright (C) 2011 Xilinx + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MACH_SYSTEM_H__ +#define __MACH_SYSTEM_H__ + +static inline void arch_idle(void) +{ + cpu_do_idle(); +} + +static inline void arch_reset(char mode, const char *cmd) +{ + /* Add architecture specific reset processing here */ +} + +#endif diff --git a/arch/arm/mach-xilinx/include/mach/timex.h b/arch/arm/mach-xilinx/include/mach/timex.h new file mode 100644 index 0000000..e82e653 --- /dev/null +++ b/arch/arm/mach-xilinx/include/mach/timex.h @@ -0,0 +1,23 @@ +/* arch/arm/mach-xilinx/include/mach/timex.h + * + * Copyright (C) 2011 Xilinx + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MACH_TIMEX_H__ +#define __MACH_TIMEX_H__ + +/* the following is needed for the system to build but will be removed + in the future, the value is not important but won't hurt +*/ +#define CLOCK_TICK_RATE (100 * HZ) + +#endif diff --git a/arch/arm/mach-xilinx/include/mach/uart.h b/arch/arm/mach-xilinx/include/mach/uart.h new file mode 100644 index 0000000..7fca361 --- /dev/null +++ b/arch/arm/mach-xilinx/include/mach/uart.h @@ -0,0 +1,25 @@ +/* arch/arm/mach-xilinx/include/mach/uart.h + * + * Copyright (C) 2011 Xilinx + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MACH_UART_H__ +#define __MACH_UART_H__ + +#define UART_CR_OFFSET 0x00 /* Control Register [8:0] */ +#define UART_SR_OFFSET 0x2C /* Channel Status [11:0] */ +#define UART_FIFO_OFFSET 0x30 /* FIFO [15:0] or [7:0] */ + +#define UART_SR_TXFULL 0x00000010 /* TX FIFO full */ +#define UART_SR_TXEMPTY 0x00000008 /* TX FIFO empty */ + +#endif diff --git a/arch/arm/mach-xilinx/include/mach/uncompress.h b/arch/arm/mach-xilinx/include/mach/uncompress.h new file mode 100644 index 0000000..ef7dd81 --- /dev/null +++ b/arch/arm/mach-xilinx/include/mach/uncompress.h @@ -0,0 +1,51 @@ +/* arch/arm/mach-xilinx/include/mach/uncompress.h + * + * Copyright (C) 2011 Xilinx + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MACH_UNCOMPRESS_H__ +#define __MACH_UNCOMPRESS_H__ + +#include <linux/io.h> +#include <asm/processor.h> +#include <mach/xilinx_soc.h> +#include <mach/uart.h> + +void arch_decomp_setup(void) +{ +} + +static inline void flush(void) +{ + /* + * Wait while the FIFO is not empty + */ + while (!(__raw_readl(IOMEM(LL_UART_PADDR + UART_SR_OFFSET)) & + UART_SR_TXEMPTY)) + cpu_relax(); +} + +#define arch_decomp_wdog() + +static void putc(char ch) +{ + /* + * Wait for room in the FIFO, then write the char into the FIFO + */ + while (__raw_readl(IOMEM(LL_UART_PADDR + UART_SR_OFFSET)) & + UART_SR_TXFULL) + cpu_relax(); + + __raw_writel(ch, IOMEM(LL_UART_PADDR + UART_FIFO_OFFSET)); +} + +#endif diff --git a/arch/arm/mach-xilinx/include/mach/vmalloc.h b/arch/arm/mach-xilinx/include/mach/vmalloc.h new file mode 100644 index 0000000..aba20a3 --- /dev/null +++ b/arch/arm/mach-xilinx/include/mach/vmalloc.h @@ -0,0 +1,20 @@ +/* arch/arm/mach-xilinx/include/mach/vmalloc.h + * + * Copyright (C) 2011 Xilinx + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MACH_VMALLOC_H__ +#define __MACH_VMALLOC_H__ + +#define VMALLOC_END 0xE0000000UL + +#endif diff --git a/arch/arm/mach-xilinx/include/mach/xilinx_soc.h b/arch/arm/mach-xilinx/include/mach/xilinx_soc.h new file mode 100644 index 0000000..d181c5c --- /dev/null +++ b/arch/arm/mach-xilinx/include/mach/xilinx_soc.h @@ -0,0 +1,48 @@ +/* arch/arm/mach-xilinx/include/mach/xilinx_soc.h + * + * Copyright (C) 2011 Xilinx + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MACH_XILINX_SOC_H__ +#define __MACH_XILINX_SOC_H__ + +#define PERIPHERAL_CLOCK_RATE 2500000 + +/* For now, all mappings are flat (physical = virtual) + */ +#define UART0_PHYS 0xE0000000 +#define UART0_VIRT UART0_PHYS + +#define TTC0_PHYS 0xF8001000 +#define TTC0_VIRT TTC0_PHYS + +#define PL310_L2CC_PHYS 0xF8F02000 +#define PL310_L2CC_VIRT PL310_L2CC_PHYS + +#define SCU_PERIPH_PHYS 0xF8F00000 +#define SCU_PERIPH_VIRT SCU_PERIPH_PHYS + +/* The following are intended for the devices that are mapped early */ + +#define TTC0_BASE IOMEM(TTC0_VIRT) +#define SCU_PERIPH_BASE IOMEM(SCU_PERIPH_VIRT) +#define SCU_GIC_CPU_BASE (SCU_PERIPH_BASE + 0x100) +#define SCU_GIC_DIST_BASE (SCU_PERIPH_BASE + 0x1000) +#define PL310_L2CC_BASE IOMEM(PL310_L2CC_VIRT) + +/* + * Mandatory for CONFIG_LL_DEBUG, UART is mapped virtual = physical + */ +#define LL_UART_PADDR UART0_PHYS +#define LL_UART_VADDR UART0_VIRT + +#endif -- 1.6.2.1 This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately. ^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH V5 3/4] ARM: Xilinx: base header files and assembly macros @ 2011-02-28 21:51 ` John Linn 0 siblings, 0 replies; 22+ messages in thread From: John Linn @ 2011-02-28 21:51 UTC (permalink / raw) To: linux-arm-kernel, linux-kernel, linux, catalin.marinas, glikely, jamie, arnd Cc: John Linn These are the minimum needed to build the kernel for the new platform. Signed-off-by: John Linn <john.linn@xilinx.com> --- V5 Changes Minor cleanup based on input from Russell King (uncompress.h.). Minor cleanup based on input from Jamie Iles (uncompress.h.). Moved to minimal dependencies on CLOCK_TICK_RATE based on input from Arnd. V4 Changes Cleanup based on input from Jamie Iles. Moved to PLAT_PHYS_OFFSET. Remove headers file inclusions that weren't needed. Added use of raw_readl/raw_writel in uncompressor uart code. Added cpu_relax() in the uncompressor uart code. V3 Changes Updates based on Russell Kings' comments Changed headers to update the license info and remove the address Updated the constant to use UL in vmalloc.h V2 Changes Updates based on Russell King's comments moved to using entry-macro-gic.S moved stuff from hardware.h to xilinx_soc.h added IOMEM() in io.h to help with typing Minor updates to IO_SPACE_LIMIT and __io() Updated addresses to be clear with seperate virtual and physical addresses arch/arm/mach-xilinx/include/mach/clkdev.h | 33 +++++++++++++++ arch/arm/mach-xilinx/include/mach/debug-macro.S | 36 ++++++++++++++++ arch/arm/mach-xilinx/include/mach/entry-macro.S | 30 +++++++++++++ arch/arm/mach-xilinx/include/mach/hardware.h | 18 ++++++++ arch/arm/mach-xilinx/include/mach/io.h | 33 +++++++++++++++ arch/arm/mach-xilinx/include/mach/irqs.h | 29 +++++++++++++ arch/arm/mach-xilinx/include/mach/memory.h | 23 ++++++++++ arch/arm/mach-xilinx/include/mach/system.h | 28 ++++++++++++ arch/arm/mach-xilinx/include/mach/timex.h | 23 ++++++++++ arch/arm/mach-xilinx/include/mach/uart.h | 25 +++++++++++ arch/arm/mach-xilinx/include/mach/uncompress.h | 51 +++++++++++++++++++++++ arch/arm/mach-xilinx/include/mach/vmalloc.h | 20 +++++++++ arch/arm/mach-xilinx/include/mach/xilinx_soc.h | 48 +++++++++++++++++++++ 13 files changed, 397 insertions(+), 0 deletions(-) create mode 100644 arch/arm/mach-xilinx/include/mach/clkdev.h create mode 100644 arch/arm/mach-xilinx/include/mach/debug-macro.S create mode 100644 arch/arm/mach-xilinx/include/mach/entry-macro.S create mode 100644 arch/arm/mach-xilinx/include/mach/hardware.h create mode 100644 arch/arm/mach-xilinx/include/mach/io.h create mode 100644 arch/arm/mach-xilinx/include/mach/irqs.h create mode 100644 arch/arm/mach-xilinx/include/mach/memory.h create mode 100644 arch/arm/mach-xilinx/include/mach/system.h create mode 100644 arch/arm/mach-xilinx/include/mach/timex.h create mode 100644 arch/arm/mach-xilinx/include/mach/uart.h create mode 100644 arch/arm/mach-xilinx/include/mach/uncompress.h create mode 100644 arch/arm/mach-xilinx/include/mach/vmalloc.h create mode 100644 arch/arm/mach-xilinx/include/mach/xilinx_soc.h diff --git a/arch/arm/mach-xilinx/include/mach/clkdev.h b/arch/arm/mach-xilinx/include/mach/clkdev.h new file mode 100644 index 0000000..5dd1453 --- /dev/null +++ b/arch/arm/mach-xilinx/include/mach/clkdev.h @@ -0,0 +1,33 @@ +/* + * arch/arm/mach-xilinx/include/mach/clkdev.h + * + * Copyright (C) 2011 Xilinx, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __MACH_CLKDEV_H__ +#define __MACH_CLKDEV_H__ + +struct clk { + unsigned long rate; +}; + +static inline int __clk_get(struct clk *clk) +{ + return 1; +} + +static inline void __clk_put(struct clk *clk) +{ +} + +#endif diff --git a/arch/arm/mach-xilinx/include/mach/debug-macro.S b/arch/arm/mach-xilinx/include/mach/debug-macro.S new file mode 100644 index 0000000..30d3d3d --- /dev/null +++ b/arch/arm/mach-xilinx/include/mach/debug-macro.S @@ -0,0 +1,36 @@ +/* arch/arm/mach-xilinx/include/mach/debug-macro.S + * + * Debugging macro include header + * + * Copyright (C) 2011 Xilinx + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <mach/xilinx_soc.h> +#include <mach/uart.h> + + .macro addruart, rp, rv + ldr \rp, =LL_UART_PADDR @ physical + ldr \rv, =LL_UART_VADDR @ virtual + .endm + + .macro senduart,rd,rx + str \rd, [\rx, #UART_FIFO_OFFSET] @ TXDATA + .endm + + .macro waituart,rd,rx + .endm + + .macro busyuart,rd,rx +1002: ldr \rd, [\rx, #UART_SR_OFFSET] @ get status register + tst \rd, #UART_SR_TXFULL @ + bne 1002b @ wait if FIFO is full + .endm diff --git a/arch/arm/mach-xilinx/include/mach/entry-macro.S b/arch/arm/mach-xilinx/include/mach/entry-macro.S new file mode 100644 index 0000000..11a2866 --- /dev/null +++ b/arch/arm/mach-xilinx/include/mach/entry-macro.S @@ -0,0 +1,30 @@ +/* + * arch/arm/mach-xilinx/include/mach/entry-macro.S + * + * Low-level IRQ helper macros + * + * Copyright (C) 2011 Xilinx + * + * based on arch/plat-mxc/include/mach/entry-macro.S + * + * Copyright (C) 2007 Lennert Buytenhek <buytenh@wantstofly.org> + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <mach/hardware.h> +#include <asm/hardware/entry-macro-gic.S> + + .macro disable_fiq + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + .endm diff --git a/arch/arm/mach-xilinx/include/mach/hardware.h b/arch/arm/mach-xilinx/include/mach/hardware.h new file mode 100644 index 0000000..f9685c4 --- /dev/null +++ b/arch/arm/mach-xilinx/include/mach/hardware.h @@ -0,0 +1,18 @@ +/* arch/arm/mach-xilinx/include/mach/hardware.h + * + * Copyright (C) 2011 Xilinx + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MACH_HARDWARE_H__ +#define __MACH_HARDWARE_H__ + +#endif diff --git a/arch/arm/mach-xilinx/include/mach/io.h b/arch/arm/mach-xilinx/include/mach/io.h new file mode 100644 index 0000000..ef69e65 --- /dev/null +++ b/arch/arm/mach-xilinx/include/mach/io.h @@ -0,0 +1,33 @@ +/* arch/arm/mach-xilinx/include/mach/io.h + * + * Copyright (C) 2011 Xilinx + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MACH_IO_H__ +#define __MACH_IO_H__ + +/* Allow IO space to be anywhere in the memory */ + +#define IO_SPACE_LIMIT 0xffff + +/* IO address mapping macros, nothing special at this time but required */ + +#ifdef __ASSEMBLER__ +#define IOMEM(x) (x) +#else +#define IOMEM(x) ((void __force __iomem *)(x)) +#endif + +#define __io(a) __typesafe_io(a) +#define __mem_pci(a) (a) + +#endif diff --git a/arch/arm/mach-xilinx/include/mach/irqs.h b/arch/arm/mach-xilinx/include/mach/irqs.h new file mode 100644 index 0000000..47a8162 --- /dev/null +++ b/arch/arm/mach-xilinx/include/mach/irqs.h @@ -0,0 +1,29 @@ +/* arch/arm/mach-xilinx/include/mach/irqs.h + * + * Copyright (C) 2011 Xilinx + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MACH_IRQS_H +#define __MACH_IRQS_H + +#define ARCH_NR_GPIOS 118 +#define NR_IRQS (128 + ARCH_NR_GPIOS) + +/* + * GIC Interrupts + */ + +#define IRQ_GIC_SPI_START 32 +#define IRQ_TIMERCOUNTER0 42 +#define IRQ_UART0 59 + +#endif diff --git a/arch/arm/mach-xilinx/include/mach/memory.h b/arch/arm/mach-xilinx/include/mach/memory.h new file mode 100644 index 0000000..b683b0e --- /dev/null +++ b/arch/arm/mach-xilinx/include/mach/memory.h @@ -0,0 +1,23 @@ +/* arch/arm/mach-xilinx/include/mach/memory.h + * + * Copyright (C) 2011 Xilinx + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MACH_MEMORY_H__ +#define __MACH_MEMORY_H__ + +#include <asm/sizes.h> + +#define PLAT_PHYS_OFFSET UL(0x0) +#define MEM_SIZE SZ_256M + +#endif diff --git a/arch/arm/mach-xilinx/include/mach/system.h b/arch/arm/mach-xilinx/include/mach/system.h new file mode 100644 index 0000000..e8514a0 --- /dev/null +++ b/arch/arm/mach-xilinx/include/mach/system.h @@ -0,0 +1,28 @@ +/* arch/arm/mach-xilinx/include/mach/system.h + * + * Copyright (C) 2011 Xilinx + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MACH_SYSTEM_H__ +#define __MACH_SYSTEM_H__ + +static inline void arch_idle(void) +{ + cpu_do_idle(); +} + +static inline void arch_reset(char mode, const char *cmd) +{ + /* Add architecture specific reset processing here */ +} + +#endif diff --git a/arch/arm/mach-xilinx/include/mach/timex.h b/arch/arm/mach-xilinx/include/mach/timex.h new file mode 100644 index 0000000..e82e653 --- /dev/null +++ b/arch/arm/mach-xilinx/include/mach/timex.h @@ -0,0 +1,23 @@ +/* arch/arm/mach-xilinx/include/mach/timex.h + * + * Copyright (C) 2011 Xilinx + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MACH_TIMEX_H__ +#define __MACH_TIMEX_H__ + +/* the following is needed for the system to build but will be removed + in the future, the value is not important but won't hurt +*/ +#define CLOCK_TICK_RATE (100 * HZ) + +#endif diff --git a/arch/arm/mach-xilinx/include/mach/uart.h b/arch/arm/mach-xilinx/include/mach/uart.h new file mode 100644 index 0000000..7fca361 --- /dev/null +++ b/arch/arm/mach-xilinx/include/mach/uart.h @@ -0,0 +1,25 @@ +/* arch/arm/mach-xilinx/include/mach/uart.h + * + * Copyright (C) 2011 Xilinx + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MACH_UART_H__ +#define __MACH_UART_H__ + +#define UART_CR_OFFSET 0x00 /* Control Register [8:0] */ +#define UART_SR_OFFSET 0x2C /* Channel Status [11:0] */ +#define UART_FIFO_OFFSET 0x30 /* FIFO [15:0] or [7:0] */ + +#define UART_SR_TXFULL 0x00000010 /* TX FIFO full */ +#define UART_SR_TXEMPTY 0x00000008 /* TX FIFO empty */ + +#endif diff --git a/arch/arm/mach-xilinx/include/mach/uncompress.h b/arch/arm/mach-xilinx/include/mach/uncompress.h new file mode 100644 index 0000000..ef7dd81 --- /dev/null +++ b/arch/arm/mach-xilinx/include/mach/uncompress.h @@ -0,0 +1,51 @@ +/* arch/arm/mach-xilinx/include/mach/uncompress.h + * + * Copyright (C) 2011 Xilinx + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MACH_UNCOMPRESS_H__ +#define __MACH_UNCOMPRESS_H__ + +#include <linux/io.h> +#include <asm/processor.h> +#include <mach/xilinx_soc.h> +#include <mach/uart.h> + +void arch_decomp_setup(void) +{ +} + +static inline void flush(void) +{ + /* + * Wait while the FIFO is not empty + */ + while (!(__raw_readl(IOMEM(LL_UART_PADDR + UART_SR_OFFSET)) & + UART_SR_TXEMPTY)) + cpu_relax(); +} + +#define arch_decomp_wdog() + +static void putc(char ch) +{ + /* + * Wait for room in the FIFO, then write the char into the FIFO + */ + while (__raw_readl(IOMEM(LL_UART_PADDR + UART_SR_OFFSET)) & + UART_SR_TXFULL) + cpu_relax(); + + __raw_writel(ch, IOMEM(LL_UART_PADDR + UART_FIFO_OFFSET)); +} + +#endif diff --git a/arch/arm/mach-xilinx/include/mach/vmalloc.h b/arch/arm/mach-xilinx/include/mach/vmalloc.h new file mode 100644 index 0000000..aba20a3 --- /dev/null +++ b/arch/arm/mach-xilinx/include/mach/vmalloc.h @@ -0,0 +1,20 @@ +/* arch/arm/mach-xilinx/include/mach/vmalloc.h + * + * Copyright (C) 2011 Xilinx + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MACH_VMALLOC_H__ +#define __MACH_VMALLOC_H__ + +#define VMALLOC_END 0xE0000000UL + +#endif diff --git a/arch/arm/mach-xilinx/include/mach/xilinx_soc.h b/arch/arm/mach-xilinx/include/mach/xilinx_soc.h new file mode 100644 index 0000000..d181c5c --- /dev/null +++ b/arch/arm/mach-xilinx/include/mach/xilinx_soc.h @@ -0,0 +1,48 @@ +/* arch/arm/mach-xilinx/include/mach/xilinx_soc.h + * + * Copyright (C) 2011 Xilinx + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MACH_XILINX_SOC_H__ +#define __MACH_XILINX_SOC_H__ + +#define PERIPHERAL_CLOCK_RATE 2500000 + +/* For now, all mappings are flat (physical = virtual) + */ +#define UART0_PHYS 0xE0000000 +#define UART0_VIRT UART0_PHYS + +#define TTC0_PHYS 0xF8001000 +#define TTC0_VIRT TTC0_PHYS + +#define PL310_L2CC_PHYS 0xF8F02000 +#define PL310_L2CC_VIRT PL310_L2CC_PHYS + +#define SCU_PERIPH_PHYS 0xF8F00000 +#define SCU_PERIPH_VIRT SCU_PERIPH_PHYS + +/* The following are intended for the devices that are mapped early */ + +#define TTC0_BASE IOMEM(TTC0_VIRT) +#define SCU_PERIPH_BASE IOMEM(SCU_PERIPH_VIRT) +#define SCU_GIC_CPU_BASE (SCU_PERIPH_BASE + 0x100) +#define SCU_GIC_DIST_BASE (SCU_PERIPH_BASE + 0x1000) +#define PL310_L2CC_BASE IOMEM(PL310_L2CC_VIRT) + +/* + * Mandatory for CONFIG_LL_DEBUG, UART is mapped virtual = physical + */ +#define LL_UART_PADDR UART0_PHYS +#define LL_UART_VADDR UART0_VIRT + +#endif -- 1.6.2.1 This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. 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[not found] <1301444651-18008-1-git-send-email-john.linn@xilinx.com>
2011-03-30 0:24 ` [PATCH V5 1/4] ARM: Xilinx: Adding Xilinx board support John Linn
2011-03-30 0:24 ` John Linn
[not found] ` <1301444651-18008-2-git-send-email-john.linn@xilinx.com>
2011-03-30 0:24 ` [PATCH V5 2/4] ARM: Xilinx: Adding timer support to the platform John Linn
2011-03-30 0:24 ` John Linn
[not found] ` <1301444651-18008-3-git-send-email-john.linn@xilinx.com>
2011-03-30 0:24 ` [PATCH V5 3/4] ARM: Xilinx: base header files and assembly macros John Linn
2011-03-30 0:24 ` John Linn
2011-03-30 11:44 ` Arnd Bergmann
2011-03-30 11:44 ` Arnd Bergmann
2011-03-30 13:17 ` John Linn
2011-03-30 13:17 ` John Linn
2011-03-30 13:29 ` Arnd Bergmann
2011-03-30 13:29 ` Arnd Bergmann
2011-03-30 13:37 ` John Linn
2011-03-30 13:37 ` John Linn
2011-03-30 19:15 ` Russell King - ARM Linux
2011-03-30 19:15 ` Russell King - ARM Linux
2011-03-30 19:43 ` Arnd Bergmann
2011-03-30 19:43 ` Arnd Bergmann
[not found] ` <1301444651-18008-4-git-send-email-john.linn@xilinx.com>
2011-03-30 0:24 ` [PATCH V5 4/4] ARM: Xilinx: Adding Xilinx platform infrastructure support John Linn
2011-03-30 0:24 ` John Linn
[not found] <1298929919-510-1-git-send-email-john.linn@xilinx.com>
[not found] ` <1298929919-510-2-git-send-email-john.linn@xilinx.com>
[not found] ` <1298929919-510-3-git-send-email-john.linn@xilinx.com>
2011-02-28 21:51 ` [PATCH V5 3/4] ARM: Xilinx: base header files and assembly macros John Linn
2011-02-28 21:51 ` John Linn
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