From: Matthew Wilcox <matthew@wil.cx>
To: "Desai, Kashyap" <Kashyap.Desai@lsi.com>
Cc: James Bottomley <James.Bottomley@HansenPartnership.com>,
"Moore, Eric" <Eric.Moore@lsi.com>,
"linux-scsi@vger.kernel.org" <linux-scsi@vger.kernel.org>,
"Prakash, Sathya" <Sathya.Prakash@lsi.com>,
benh@kernel.crashing.org, paulus@samba.org,
linuxppc-dev@lists.ozlabs.org
Subject: Re: [PATCH 1/3] mpt2sas: remove the use of writeq, since writeq is not atomic
Date: Tue, 17 May 2011 22:15:52 -0600 [thread overview]
Message-ID: <20110518041551.GL15227@parisc-linux.org> (raw)
In-Reply-To: <B2FD678A64EAAD45B089B123FDFC3ED70157F7BCE5@inbmail01.lsi.com>
On Wed, May 18, 2011 at 09:37:08AM +0530, Desai, Kashyap wrote:
> On Wed, 2011-05-04 at 17:23 +0530, Kashyap, Desai wrote:
> > The following code seems to be there in /usr/src/linux/arch/x86/include/asm/io.h.
> > This is not going to work.
> >
> > static inline void writeq(__u64 val, volatile void __iomem *addr)
> > {
> > writel(val, addr);
> > writel(val >> 32, addr+4);
> > }
> >
> > So with this code turned on in the kernel, there is going to be race condition
> > where multiple cpus can be writing to the request descriptor at the same time.
> >
> > Meaning this could happen:
> > (A) CPU A doest 32bit write
> > (B) CPU B does 32 bit write
> > (C) CPU A does 32 bit write
> > (D) CPU B does 32 bit write
> >
> > We need the 64 bit completed in one access pci memory write, else spin lock is required.
> > Since it's going to be difficult to know which writeq was implemented in the kernel,
> > the driver is going to have to always acquire a spin lock each time we do 64bit write.
> >
> > Cc: stable@kernle.org
> > Signed-off-by: Kashyap Desai <kashyap.desai@lsi.com>
> > ---
> > diff --git a/drivers/scsi/mpt2sas/mpt2sas_base.c b/drivers/scsi/mpt2sas/mpt2sas_base.c
> > index efa0255..5778334 100644
> > --- a/drivers/scsi/mpt2sas/mpt2sas_base.c
> > +++ b/drivers/scsi/mpt2sas/mpt2sas_base.c
> > @@ -1558,7 +1558,6 @@ mpt2sas_base_free_smid(struct MPT2SAS_ADAPTER *ioc, u16 smid)
> > * care of 32 bit environment where its not quarenteed to send the entire word
> > * in one transfer.
> > */
> > -#ifndef writeq
>
> Why not make this #ifndef CONFIG_64BIT? You know that all 64 bit
> systems have writeq implemented correctly; you suspect 32 bit systems
> don't.
>
> James
>
> James, This issue was observed on PPC64 system. So what you have suggested will not solve this issue.
> If we are sure that writeq() is atomic across all architecture, we can use it safely. As we have seen issue on ppc64, we are not confident to use
> "writeq" call.
So have you told the powerpc people that they have a broken writeq?
And why do you obfuscate your report by talking about i386 when it's
really about powerpc64?
--
Matthew Wilcox Intel Open Source Technology Centre
"Bill, look, we understand that you're interested in selling us this
operating system, but compare it to ours. We can't possibly take such
a retrograde step."
WARNING: multiple messages have this Message-ID (diff)
From: Matthew Wilcox <matthew@wil.cx>
To: "Desai, Kashyap" <Kashyap.Desai@lsi.com>
Cc: "Prakash, Sathya" <Sathya.Prakash@lsi.com>,
"linux-scsi@vger.kernel.org" <linux-scsi@vger.kernel.org>,
linuxppc-dev@lists.ozlabs.org,
James Bottomley <James.Bottomley@HansenPartnership.com>,
paulus@samba.org, "Moore, Eric" <Eric.Moore@lsi.com>
Subject: Re: [PATCH 1/3] mpt2sas: remove the use of writeq, since writeq is not atomic
Date: Tue, 17 May 2011 22:15:52 -0600 [thread overview]
Message-ID: <20110518041551.GL15227@parisc-linux.org> (raw)
In-Reply-To: <B2FD678A64EAAD45B089B123FDFC3ED70157F7BCE5@inbmail01.lsi.com>
On Wed, May 18, 2011 at 09:37:08AM +0530, Desai, Kashyap wrote:
> On Wed, 2011-05-04 at 17:23 +0530, Kashyap, Desai wrote:
> > The following code seems to be there in /usr/src/linux/arch/x86/include/asm/io.h.
> > This is not going to work.
> >
> > static inline void writeq(__u64 val, volatile void __iomem *addr)
> > {
> > writel(val, addr);
> > writel(val >> 32, addr+4);
> > }
> >
> > So with this code turned on in the kernel, there is going to be race condition
> > where multiple cpus can be writing to the request descriptor at the same time.
> >
> > Meaning this could happen:
> > (A) CPU A doest 32bit write
> > (B) CPU B does 32 bit write
> > (C) CPU A does 32 bit write
> > (D) CPU B does 32 bit write
> >
> > We need the 64 bit completed in one access pci memory write, else spin lock is required.
> > Since it's going to be difficult to know which writeq was implemented in the kernel,
> > the driver is going to have to always acquire a spin lock each time we do 64bit write.
> >
> > Cc: stable@kernle.org
> > Signed-off-by: Kashyap Desai <kashyap.desai@lsi.com>
> > ---
> > diff --git a/drivers/scsi/mpt2sas/mpt2sas_base.c b/drivers/scsi/mpt2sas/mpt2sas_base.c
> > index efa0255..5778334 100644
> > --- a/drivers/scsi/mpt2sas/mpt2sas_base.c
> > +++ b/drivers/scsi/mpt2sas/mpt2sas_base.c
> > @@ -1558,7 +1558,6 @@ mpt2sas_base_free_smid(struct MPT2SAS_ADAPTER *ioc, u16 smid)
> > * care of 32 bit environment where its not quarenteed to send the entire word
> > * in one transfer.
> > */
> > -#ifndef writeq
>
> Why not make this #ifndef CONFIG_64BIT? You know that all 64 bit
> systems have writeq implemented correctly; you suspect 32 bit systems
> don't.
>
> James
>
> James, This issue was observed on PPC64 system. So what you have suggested will not solve this issue.
> If we are sure that writeq() is atomic across all architecture, we can use it safely. As we have seen issue on ppc64, we are not confident to use
> "writeq" call.
So have you told the powerpc people that they have a broken writeq?
And why do you obfuscate your report by talking about i386 when it's
really about powerpc64?
--
Matthew Wilcox Intel Open Source Technology Centre
"Bill, look, we understand that you're interested in selling us this
operating system, but compare it to ours. We can't possibly take such
a retrograde step."
next prev parent reply other threads:[~2011-05-18 4:15 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-05-04 11:53 [PATCH 1/3] mpt2sas: remove the use of writeq, since writeq is not atomic Kashyap, Desai
2011-05-17 7:16 ` James Bottomley
2011-05-18 4:07 ` Desai, Kashyap
2011-05-18 4:15 ` Matthew Wilcox [this message]
2011-05-18 4:15 ` Matthew Wilcox
2011-05-18 4:23 ` James Bottomley
2011-05-18 4:23 ` James Bottomley
2011-05-18 7:00 ` Benjamin Herrenschmidt
2011-05-18 7:00 ` Benjamin Herrenschmidt
2011-05-18 8:23 ` Milton Miller
2011-05-18 8:23 ` Milton Miller
2011-05-18 15:35 ` Moore, Eric
2011-05-18 15:35 ` Moore, Eric
2011-05-18 18:31 ` Milton Miller
2011-05-18 18:31 ` Milton Miller
2011-05-18 18:31 ` Milton Miller
2011-05-18 19:11 ` Moore, Eric
2011-05-18 19:11 ` Moore, Eric
2011-05-18 19:11 ` Moore, Eric
2011-05-19 4:08 ` Hitoshi Mitake
2011-05-19 4:08 ` Hitoshi Mitake
2011-05-19 4:46 ` James Bottomley
2011-05-19 4:46 ` James Bottomley
2011-05-19 5:36 ` Benjamin Herrenschmidt
2011-05-19 5:36 ` Benjamin Herrenschmidt
2011-05-19 8:35 ` [PATCH 1/3] mpt2sas: remove the use of writeq, since writeq isnot atomic David Laight
2011-05-19 8:35 ` David Laight
2011-05-19 8:35 ` David Laight
2011-05-19 4:16 ` [PATCH 1/3] mpt2sas: remove the use of writeq, since writeq is not atomic Roland Dreier
2011-05-19 4:16 ` Roland Dreier
2011-05-19 5:34 ` Benjamin Herrenschmidt
2011-05-19 5:34 ` Benjamin Herrenschmidt
2011-05-19 18:15 ` Ingo Molnar
2011-05-19 18:15 ` Ingo Molnar
2011-05-19 23:54 ` [PATCH] x86: Remove 32-bit versions of readq()/writeq() Roland Dreier
2011-05-20 1:15 ` Hitoshi Mitake
2011-05-20 8:05 ` Desai, Kashyap
2011-05-20 11:44 ` Ingo Molnar
2011-05-20 12:03 ` James Bottomley
2011-05-18 21:30 ` [PATCH 1/3] mpt2sas: remove the use of writeq, since writeq is not atomic Benjamin Herrenschmidt
2011-05-18 22:05 ` Moore, Eric
2011-05-18 22:05 ` Moore, Eric
2011-05-18 8:04 ` [PATCH 1/3] mpt2sas: remove the use of writeq, since writeq isnot atomic David Laight
2011-05-18 8:04 ` David Laight
2011-05-18 5:45 ` [PATCH 1/3] mpt2sas: remove the use of writeq, since writeq is not atomic Benjamin Herrenschmidt
2011-05-18 5:45 ` Benjamin Herrenschmidt
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20110518041551.GL15227@parisc-linux.org \
--to=matthew@wil.cx \
--cc=Eric.Moore@lsi.com \
--cc=James.Bottomley@HansenPartnership.com \
--cc=Kashyap.Desai@lsi.com \
--cc=Sathya.Prakash@lsi.com \
--cc=benh@kernel.crashing.org \
--cc=linux-scsi@vger.kernel.org \
--cc=linuxppc-dev@lists.ozlabs.org \
--cc=paulus@samba.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.