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From: Pavel Machek <pma@sysgo.com>
To: Richard Zhu <richard.zhu@linaro.org>,
	linux-arm-kernel@lists.infradead.org, cjb@laptop.org,
	linux-mmc@vger.kernel.org, w.sang@pengutronix.de,
	eric.miao@linaro.org, kernel@pengutronix.
Cc: pba@sysgo.com
Subject: Re: [PATCH V2] mmc: Enable the ADMA on esdhc imx driver
Date: Thu, 16 Jun 2011 13:51:33 +0200	[thread overview]
Message-ID: <20110616115133.GC31375@pma.sysgo.com> (raw)
In-Reply-To: <20110615082223.GA28798@atrey.karlin.mff.cuni.cz>

Hi!

> Eanble the ADMA2 mode on freescale esdhc imx driver,
> tested on MX51 and MX53.
> 
> Only ADMA2 mode is enabled, MX25/35 can't support the ADMA2 mode.
> So this patch is only used for MX51/53.
> The ADMA2 mode supported or not can be distinguished by the
> Capability Register(offset 0x40) of eSDHC module.
> Up to now, only MX51/MX53 set the ADMA2 supported bit(Bit20) in the
> Capability Register.

I tried it on mx25 (3-stack), and it unfortunately breaks things:

...
mmc0: unrecognised SCR structure version 12
mmc0: error -22 whilst initialising SD card
...

It may be interfering with my changs, but... 

> +/*
> + * There is INT DMA ERR mis-match between eSDHC and STD SDHC SPEC
> + * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design,
> + * but bit28 is used as the INT DMA ERR in fsl eSDHC design.
> + * Define this macro DMA error INT for fsl eSDHC
> + */
> +#define  SDHCI_INT_VENDOR_SPEC_DMA_ERR	0x10000000
> +
>  #define ESDHC_FLAG_GPIO_FOR_CD_WP	(1 << 0)
>  /*
>   * The CMDTYPE of the CMD register (offset 0xE) should be set to
> @@ -80,6 +88,20 @@ static u32 esdhc_readl_le(struct sdhci_host *host, int reg)
>  			val |= SDHCI_CARD_PRESENT;
>  	}
>  
> +	if (unlikely(reg == SDHCI_CAPABILITIES)) {
> +		if (val & SDHCI_CAN_DO_ADMA1) {
> +			val &= ~SDHCI_CAN_DO_ADMA1;
> +			val |= SDHCI_CAN_DO_ADMA2;
> +		}
> +	}
> +
> +	if (unlikely(reg == SDHCI_INT_STATUS)) {
> +		if (val & SDHCI_INT_VENDOR_SPEC_DMA_ERR) {
> +			val &= ~SDHCI_INT_VENDOR_SPEC_DMA_ERR;
> +			val |= SDHCI_INT_ADMA_ERROR;
> +		}
> +	}
> +
>  	return val;
>  }
>

Unfortunately register differences are common. Is there better
approach than patching it in low level functions like this?

> @@ -322,9 +351,10 @@ static void esdhc_pltfm_exit(struct sdhci_host *host)
>  }
>  
>  struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = {
> -	.quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_BROKEN_ADMA
> +	.quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_HISPD_BIT
> +			| SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
> +			| SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC
>  			| SDHCI_QUIRK_BROKEN_CARD_DETECTION,

If I re-add "SDHCI_QUIRK_BROKEN_ADMA", it starts working.

								Pavel

WARNING: multiple messages have this Message-ID (diff)
From: pma@sysgo.com (Pavel Machek)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH V2] mmc: Enable the ADMA on esdhc imx driver
Date: Thu, 16 Jun 2011 13:51:33 +0200	[thread overview]
Message-ID: <20110616115133.GC31375@pma.sysgo.com> (raw)
In-Reply-To: <20110615082223.GA28798@atrey.karlin.mff.cuni.cz>

Hi!

> Eanble the ADMA2 mode on freescale esdhc imx driver,
> tested on MX51 and MX53.
> 
> Only ADMA2 mode is enabled, MX25/35 can't support the ADMA2 mode.
> So this patch is only used for MX51/53.
> The ADMA2 mode supported or not can be distinguished by the
> Capability Register(offset 0x40) of eSDHC module.
> Up to now, only MX51/MX53 set the ADMA2 supported bit(Bit20) in the
> Capability Register.

I tried it on mx25 (3-stack), and it unfortunately breaks things:

...
mmc0: unrecognised SCR structure version 12
mmc0: error -22 whilst initialising SD card
...

It may be interfering with my changs, but... 

> +/*
> + * There is INT DMA ERR mis-match between eSDHC and STD SDHC SPEC
> + * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design,
> + * but bit28 is used as the INT DMA ERR in fsl eSDHC design.
> + * Define this macro DMA error INT for fsl eSDHC
> + */
> +#define  SDHCI_INT_VENDOR_SPEC_DMA_ERR	0x10000000
> +
>  #define ESDHC_FLAG_GPIO_FOR_CD_WP	(1 << 0)
>  /*
>   * The CMDTYPE of the CMD register (offset 0xE) should be set to
> @@ -80,6 +88,20 @@ static u32 esdhc_readl_le(struct sdhci_host *host, int reg)
>  			val |= SDHCI_CARD_PRESENT;
>  	}
>  
> +	if (unlikely(reg == SDHCI_CAPABILITIES)) {
> +		if (val & SDHCI_CAN_DO_ADMA1) {
> +			val &= ~SDHCI_CAN_DO_ADMA1;
> +			val |= SDHCI_CAN_DO_ADMA2;
> +		}
> +	}
> +
> +	if (unlikely(reg == SDHCI_INT_STATUS)) {
> +		if (val & SDHCI_INT_VENDOR_SPEC_DMA_ERR) {
> +			val &= ~SDHCI_INT_VENDOR_SPEC_DMA_ERR;
> +			val |= SDHCI_INT_ADMA_ERROR;
> +		}
> +	}
> +
>  	return val;
>  }
>

Unfortunately register differences are common. Is there better
approach than patching it in low level functions like this?

> @@ -322,9 +351,10 @@ static void esdhc_pltfm_exit(struct sdhci_host *host)
>  }
>  
>  struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = {
> -	.quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_BROKEN_ADMA
> +	.quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_HISPD_BIT
> +			| SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
> +			| SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC
>  			| SDHCI_QUIRK_BROKEN_CARD_DETECTION,

If I re-add "SDHCI_QUIRK_BROKEN_ADMA", it starts working.

								Pavel

       reply	other threads:[~2011-06-16 11:51 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <20110615082223.GA28798@atrey.karlin.mff.cuni.cz>
2011-06-16 11:51 ` Pavel Machek [this message]
2011-06-16 11:51   ` [PATCH V2] mmc: Enable the ADMA on esdhc imx driver Pavel Machek
2011-06-16 12:00   ` Wolfram Sang
2011-06-16 12:00     ` Wolfram Sang
2011-06-16 12:06     ` Pavel Machek
2011-06-16 12:06       ` Pavel Machek
2011-06-16 12:19       ` Wolfram Sang
2011-06-16 12:19         ` Wolfram Sang
     [not found]   ` <BANLkTi=JHnv+_HwkqR+LEq4no70abVKksw@mail.gmail.com>
2011-06-17  7:48     ` Wolfram Sang
2011-06-17  7:48       ` Wolfram Sang
2011-06-09  5:37 Richard Zhu
2011-06-09  5:37 ` Richard Zhu

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