[U-Boot] [PATCH v3 0/6] Add cache line alignment support

[U-Boot] [PATCH v3 0/6] Add cache line alignment support

[Anton Staaf]

The cache line alignment issue has gone around a couple of times now.  This
patch set implements all of the details that we have discussed about the
implementation of ALLOC_CACHE_ALIGN_BUFFER.  It also includes patches that use
the macro to fix MMC and ext2 buffers, as well as define the
CONFIG_SYS_CACHELINE_SIZE value for Tegra.

This series now depends on the series to add ARCH_DMA_MINALIGN for all
architectures and must be applied after that series.

This has been tested on a Seaboard.

Thanks,
    Anton

---

Changes for v2:
- Add comment describing why we are setting a default cacheline size
- Remove Gerrit generated Change-Id: tags from commit messages
- Add additional buffer alignments for mmc and part_efi code

Changes for v3:
- Don't set a default value for CONFIG_SYS_CACHELINE_SIZE
- Use ARCH_DMA_MINALIGN to align DMA buffers

Anton Staaf (6):
  cache: add ALLOC_CACHE_ALIGN_BUFFER macro
  tegra: define CONFIG_SYS_CACHELINE_SIZE for tegra
  mmc: dcache: allocate cache aligned buffer for scr and switch_status
  ext2: Cache line aligned partial sector bounce buffer
  mmc: dcache: allocate cache aligned buffers for ext_csd
  part_efi: dcache: allocate cacheline aligned buffers

 disk/part_efi.c                 |   18 ++++++------
 doc/README.arm-caches           |    2 +
 drivers/mmc/mmc.c               |   14 +++++-----
 fs/ext2/dev.c                   |    2 +-
 include/common.h                |   58 +++++++++++++++++++++++++++++++++++++++
 include/configs/tegra2-common.h |    2 +
 6 files changed, 79 insertions(+), 17 deletions(-)

-- 
1.7.3.1

[U-Boot] [PATCH v3 1/6] cache: add ALLOC_CACHE_ALIGN_BUFFER macro

[Anton Staaf]

This macro is used to allocate cache line size aligned stack
buffers for use with DMA hardware.

Signed-off-by: Anton Staaf <robotboy@chromium.org>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Aneesh V <aneesh@ti.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Wolfgang Denk <wd@denx.de>
---
 doc/README.arm-caches |    2 +
 include/common.h      |   58 +++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 60 insertions(+), 0 deletions(-)

diff --git a/doc/README.arm-caches b/doc/README.arm-caches
index cd2b458..f6a52e3 100644
--- a/doc/README.arm-caches
+++ b/doc/README.arm-caches
@@ -40,6 +40,8 @@ Buffer Requirements:
 - If the buffer is not cache-line aligned invalidation will be restricted
   to the aligned part. That is, one cache-line at the respective boundary
   may be left out while doing invalidation.
+- A suitable buffer can be alloced on the stack using the
+  ALLOC_CACHE_ALIGN_BUFFER macro.
 
 Cleanup Before Linux:
 - cleanup_before_linux() should flush the D-cache, invalidate I-cache, and
diff --git a/include/common.h b/include/common.h
index 74e41d4..038d34d 100644
--- a/include/common.h
+++ b/include/common.h
@@ -822,6 +822,64 @@ int cpu_release(int nr, int argc, char * const argv[]);
 #include <asm/cache.h>
 #endif
 
+/*
+ * The ALLOC_CACHE_ALIGN_BUFFER macro is used to allocate a buffer on the
+ * stack that meets the minimum architecture alignment requirements for DMA.
+ * Such a buffer is useful for DMA operations where flushing and invalidating
+ * the cache before and after a read and/or write operation is required for
+ * correct operations.
+ *
+ * When called the macro creates an array on the stack that is sized such
+ * that:
+ *
+ * 1) The beginning of the array can be advanced enough to be aligned.
+ *
+ * 2) The size of the aligned portion of the array is a multiple of the minimum
+ *    architecture alignment required for DMA.
+ *
+ * 3) The aligned portion contains enough space for the original number of
+ *    elements requested.
+ *
+ * The macro then creates a pointer to the aligned portion of this array and
+ * assigns to the pointer the address of the first element in the aligned
+ * portion of the array.
+ *
+ * Calling the macro as:
+ *
+ *     ALLOC_CACHE_ALIGN_BUFFER(uint32_t, buffer, 1024);
+ *
+ * Will result in something similar to saying:
+ *
+ *     uint32_t    buffer[1024];
+ *
+ * The following differences exist:
+ *
+ * 1) The resulting buffer is guaranteed to be aligned to the value of
+ *    ARCH_DMA_MINALIGN.
+ *
+ * 2) The buffer variable created by the macro is a pointer to the specified
+ *    type, and NOT an array of the specified type.  This can be very important
+ *    if you want the address of the buffer, which you probably do, to pass it
+ *    to the DMA hardware.  The value of &buffer is different in the two cases.
+ *    In the macro case it will be the address of the pointer, not the address
+ *    of the space reserved for the buffer.  However, in the second case it
+ *    would be the address of the buffer.  So if you are replacing hard coded
+ *    stack buffers with this macro you need to make sure you remove the & from
+ *    the locations where you are taking the address of the buffer.
+ *
+ * Note that the size parameter is the number of array elements to allocate,
+ * not the number of bytes.
+ *
+ * This macro can not be used outside of function scope, or for the creation
+ * of a function scoped static buffer.  It can not be used to create a cache
+ * line aligned global buffer.
+ */
+#define ALLOC_CACHE_ALIGN_BUFFER(type, name, size)			\
+	char __##name[ROUND(size * sizeof(type), ARCH_DMA_MINALIGN) +	\
+		      ARCH_DMA_MINALIGN - 1];				\
+									\
+	type *name = (type *) ALIGN((uintptr_t)__##name, ARCH_DMA_MINALIGN)
+
 /* Pull in stuff for the build system */
 #ifdef DO_DEPS_ONLY
 # include <environment.h>
-- 
1.7.3.1

[U-Boot] [PATCH v3 2/6] tegra: define CONFIG_SYS_CACHELINE_SIZE for tegra

[Anton Staaf]

Signed-off-by: Anton Staaf <robotboy@chromium.org>
Cc: Tom Warren <twarren.nvidia@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
---
 include/configs/tegra2-common.h |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/include/configs/tegra2-common.h b/include/configs/tegra2-common.h
index 73e0f05..a9c665c 100644
--- a/include/configs/tegra2-common.h
+++ b/include/configs/tegra2-common.h
@@ -33,6 +33,8 @@
 #define CONFIG_MACH_TEGRA_GENERIC	/* which is a Tegra generic machine */
 #define CONFIG_SYS_L2CACHE_OFF		/* No L2 cache */
 
+#define CONFIG_SYS_CACHELINE_SIZE	32
+
 #define CONFIG_ENABLE_CORTEXA9		/* enable CPU (A9 complex) */
 
 #include <asm/arch/tegra2.h>		/* get chip and board defs */
-- 
1.7.3.1

[U-Boot] [PATCH v3 3/6] mmc: dcache: allocate cache aligned buffer for scr and switch_status

[Anton Staaf]

Currently the sd_change_freq function allocates two buffers on the
stack that it passes down to the MMC device driver.  These buffers
could be unaligned to the L1 dcache line size.  This causes problems
when using DMA and with caches enabled.

This patch correctly cache alignes the buffers used for reading the
scr register and switch status values from an MMC device.

Signed-off-by: Anton Staaf <robotboy@chromium.org>
Acked-by: Mike Frysinger <vapier@gentoo.org>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
---
 drivers/mmc/mmc.c |   10 +++++-----
 1 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 391bc2b..ba6fbfe 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -702,8 +702,8 @@ int sd_change_freq(struct mmc *mmc)
 {
 	int err;
 	struct mmc_cmd cmd;
-	uint scr[2];
-	uint switch_status[16];
+	ALLOC_CACHE_ALIGN_BUFFER(uint, scr, 2);
+	ALLOC_CACHE_ALIGN_BUFFER(uint, switch_status, 16);
 	struct mmc_data data;
 	int timeout;
 
@@ -731,7 +731,7 @@ int sd_change_freq(struct mmc *mmc)
 	timeout = 3;
 
 retry_scr:
-	data.dest = (char *)&scr;
+	data.dest = (char *)scr;
 	data.blocksize = 8;
 	data.blocks = 1;
 	data.flags = MMC_DATA_READ;
@@ -773,7 +773,7 @@ retry_scr:
 	timeout = 4;
 	while (timeout--) {
 		err = sd_switch(mmc, SD_SWITCH_CHECK, 0, 1,
-				(u8 *)&switch_status);
+				(u8 *)switch_status);
 
 		if (err)
 			return err;
@@ -787,7 +787,7 @@ retry_scr:
 	if (!(__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED))
 		return 0;
 
-	err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, 1, (u8 *)&switch_status);
+	err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, 1, (u8 *)switch_status);
 
 	if (err)
 		return err;
-- 
1.7.3.1

[U-Boot] [PATCH v3 4/6] ext2: Cache line aligned partial sector bounce buffer

[Anton Staaf]

Currently, if a device read request is done that does not begin or end
on a sector boundary a stack allocated bounce buffer is used to perform
the read, and then just the part of the sector that is needed is copied
into the users buffer.  This stack allocation can mean that the bounce
buffer will not be aligned to the dcache line size.  This is a problem
when caches are enabled because unaligned cache invalidates are not
safe.

This patch uses ALLOC_CACHE_ALIGN_BUFFER to create a stack allocated
cache line size aligned bounce buffer.

Signed-off-by: Anton Staaf <robotboy@chromium.org>
Acked-by: Mike Frysinger <vapier@gentoo.org>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Dave Liu <r63238@freescale.com>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
---
 fs/ext2/dev.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/fs/ext2/dev.c b/fs/ext2/dev.c
index 78851d0..874e211 100644
--- a/fs/ext2/dev.c
+++ b/fs/ext2/dev.c
@@ -52,7 +52,7 @@ int ext2fs_set_blk_dev(block_dev_desc_t *rbdd, int part)
 
 int ext2fs_devread(int sector, int byte_offset, int byte_len, char *buf)
 {
-	char sec_buf[SECTOR_SIZE];
+	ALLOC_CACHE_ALIGN_BUFFER(char, sec_buf, SECTOR_SIZE);
 	unsigned sectors;
 
 	/*
-- 
1.7.3.1

[U-Boot] [PATCH v3 5/6] mmc: dcache: allocate cache aligned buffers for ext_csd

[Anton Staaf]

Currently the mmc_change_freq and mmc_startup functions allocates
buffers on the stack that are passed down to the MMC device driver.
These buffers could be unaligned to the L1 dcache line size.  This
causes problems when using DMA and with caches enabled.

This patch correctly cache alignes the buffers used for reading the
ext_csd data from an MMC device.

Signed-off-by: Anton Staaf <robotboy@chromium.org>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
---
 drivers/mmc/mmc.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index ba6fbfe..e5fedb3 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -618,7 +618,7 @@ int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value)
 
 int mmc_change_freq(struct mmc *mmc)
 {
-	char ext_csd[512];
+	ALLOC_CACHE_ALIGN_BUFFER(char, ext_csd, 512);
 	char cardtype;
 	int err;
 
@@ -860,7 +860,7 @@ int mmc_startup(struct mmc *mmc)
 	uint mult, freq;
 	u64 cmult, csize, capacity;
 	struct mmc_cmd cmd;
-	char ext_csd[512];
+	ALLOC_CACHE_ALIGN_BUFFER(char, ext_csd, 512);
 	int timeout = 1000;
 
 #ifdef CONFIG_MMC_SPI_CRC_ON
-- 
1.7.3.1

[U-Boot] [PATCH v3 6/6] part_efi: dcache: allocate cacheline aligned buffers

[Anton Staaf]

Currently part_efi.c allocates buffers for the gpt_header, the
legacy_mbr, and the pte (partition table entry) that may be
incorrectly aligned for DMA operations.

This patch uses ALLOC_CACHE_ALIGN_BUFFER for the stack allocated
buffers and memalign to replace the malloc of the pte.

Signed-off-by: Anton Staaf <robotboy@chromium.org>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
---
 disk/part_efi.c |   18 +++++++++---------
 1 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/disk/part_efi.c b/disk/part_efi.c
index 0a513c6..e591724 100644
--- a/disk/part_efi.c
+++ b/disk/part_efi.c
@@ -120,7 +120,7 @@ static char *print_efiname(gpt_entry *pte)
 
 void print_part_efi(block_dev_desc_t * dev_desc)
 {
-	gpt_header gpt_head;
+	ALLOC_CACHE_ALIGN_BUFFER(gpt_header, gpt_head, 1);
 	gpt_entry **pgpt_pte = NULL;
 	int i = 0;
 
@@ -130,7 +130,7 @@ void print_part_efi(block_dev_desc_t * dev_desc)
 	}
 	/* This function validates AND fills in the GPT header and PTE */
 	if (is_gpt_valid(dev_desc, GPT_PRIMARY_PARTITION_TABLE_LBA,
-			 &(gpt_head), pgpt_pte) != 1) {
+			 gpt_head, pgpt_pte) != 1) {
 		printf("%s: *** ERROR: Invalid GPT ***\n", __FUNCTION__);
 		return;
 	}
@@ -138,7 +138,7 @@ void print_part_efi(block_dev_desc_t * dev_desc)
 	debug("%s: gpt-entry at 0x%08X\n", __FUNCTION__, (unsigned int)*pgpt_pte);
 
 	printf("Part\tName\t\t\tStart LBA\tEnd LBA\n");
-	for (i = 0; i < le32_to_int(gpt_head.num_partition_entries); i++) {
+	for (i = 0; i < le32_to_int(gpt_head->num_partition_entries); i++) {
 
 		if (is_pte_valid(&(*pgpt_pte)[i])) {
 			printf("%3d\t%-18s\t0x%08llX\t0x%08llX\n", (i + 1),
@@ -161,7 +161,7 @@ void print_part_efi(block_dev_desc_t * dev_desc)
 int get_partition_info_efi(block_dev_desc_t * dev_desc, int part,
 				disk_partition_t * info)
 {
-	gpt_header gpt_head;
+	ALLOC_CACHE_ALIGN_BUFFER(gpt_header, gpt_head, 1);
 	gpt_entry **pgpt_pte = NULL;
 
 	/* "part" argument must be at least 1 */
@@ -172,7 +172,7 @@ int get_partition_info_efi(block_dev_desc_t * dev_desc, int part,
 
 	/* This function validates AND fills in the GPT header and PTE */
 	if (is_gpt_valid(dev_desc, GPT_PRIMARY_PARTITION_TABLE_LBA,
-			&(gpt_head), pgpt_pte) != 1) {
+			 gpt_head, pgpt_pte) != 1) {
 		printf("%s: *** ERROR: Invalid GPT ***\n", __FUNCTION__);
 		return -1;
 	}
@@ -201,11 +201,11 @@ int get_partition_info_efi(block_dev_desc_t * dev_desc, int part,
 
 int test_part_efi(block_dev_desc_t * dev_desc)
 {
-	legacy_mbr legacymbr;
+	ALLOC_CACHE_ALIGN_BUFFER(legacy_mbr, legacymbr, 1);
 
 	/* Read legacy MBR from block 0 and validate it */
-	if ((dev_desc->block_read(dev_desc->dev, 0, 1, (ulong *) & legacymbr) != 1)
-		|| (is_pmbr_valid(&legacymbr) != 1)) {
+	if ((dev_desc->block_read(dev_desc->dev, 0, 1, (ulong *)legacymbr) != 1)
+		|| (is_pmbr_valid(legacymbr) != 1)) {
 		return -1;
 	}
 	return 0;
@@ -388,7 +388,7 @@ static gpt_entry *alloc_read_gpt_entries(block_dev_desc_t * dev_desc,
 
 	/* Allocate memory for PTE, remember to FREE */
 	if (count != 0) {
-		pte = malloc(count);
+		pte = memalign(CONFIG_SYS_CACHELINE_SIZE, count);
 	}
 
 	if (count == 0 || pte == NULL) {
-- 
1.7.3.1

[U-Boot] [PATCH v3 1/6] cache: add ALLOC_CACHE_ALIGN_BUFFER macro

[Mike Frysinger]

On Wednesday 12 October 2011 19:55:59 Anton Staaf wrote:
>  doc/README.arm-caches |    2 +

seems like most of the advice in this is arch independent
-mike
-------------- next part --------------
A non-text attachment was scrubbed...
Name: not available
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part.
Url : http://lists.denx.de/pipermail/u-boot/attachments/20111012/88f74d7d/attachment.pgp 

[U-Boot] [PATCH v3 3/6] mmc: dcache: allocate cache aligned buffer for scr and switch_status

[Mike Frysinger]

built fine for me
Acked-by: Mike Frysinger <vapier@gentoo.org>
-mike
-------------- next part --------------
A non-text attachment was scrubbed...
Name: not available
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part.
Url : http://lists.denx.de/pipermail/u-boot/attachments/20111012/8d18da82/attachment.pgp 

[U-Boot] [PATCH v3 5/6] mmc: dcache: allocate cache aligned buffers for ext_csd

[Mike Frysinger]

Acked-by: Mike Frysinger <vapier@gentoo.org>
-mike
-------------- next part --------------
A non-text attachment was scrubbed...
Name: not available
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part.
Url : http://lists.denx.de/pipermail/u-boot/attachments/20111012/fa933bf0/attachment.pgp 

[U-Boot] [PATCH v3 6/6] part_efi: dcache: allocate cacheline aligned buffers

[Mike Frysinger]

Acked-by: Mike Frysinger <vapier@gentoo.org>
-mike
-------------- next part --------------
A non-text attachment was scrubbed...
Name: not available
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part.
Url : http://lists.denx.de/pipermail/u-boot/attachments/20111012/c0a7bbe0/attachment.pgp 

[U-Boot] [PATCH v3 1/6] cache: add ALLOC_CACHE_ALIGN_BUFFER macro

[Anton Staaf]

On Wed, Oct 12, 2011 at 5:55 PM, Mike Frysinger <vapier@gentoo.org> wrote:
> On Wednesday 12 October 2011 19:55:59 Anton Staaf wrote:
>> ?doc/README.arm-caches | ? ?2 +
>
> seems like most of the advice in this is arch independent

Agreed.  It probably makes sense to change the name of the file.  I'm not
sure that any of it's contents should be ARM specific moving forward.  That
is, it reflects where all of the supported architectures should go yes?

-Anton

> -mike
>

[U-Boot] [PATCH v3 1/6] cache: add ALLOC_CACHE_ALIGN_BUFFER macro

[Mike Frysinger]

On Thursday 13 October 2011 14:06:41 Anton Staaf wrote:
> On Wed, Oct 12, 2011 at 5:55 PM, Mike Frysinger wrote:
> > On Wednesday 12 October 2011 19:55:59 Anton Staaf wrote:
> >>  doc/README.arm-caches |    2 +
> > 
> > seems like most of the advice in this is arch independent
> 
> Agreed.  It probably makes sense to change the name of the file.  I'm not
> sure that any of it's contents should be ARM specific moving forward.  That
> is, it reflects where all of the supported architectures should go yes?

hmm, i thought you were adding this file, not updating it

the enable_caches() part is ARM specific, as is the Cleanup Before Linux.  but 
the rest should be in like README.caches.
-mike
-------------- next part --------------
A non-text attachment was scrubbed...
Name: not available
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part.
Url : http://lists.denx.de/pipermail/u-boot/attachments/20111013/3deda6dd/attachment.pgp 

[U-Boot] [PATCH v3 1/6] cache: add ALLOC_CACHE_ALIGN_BUFFER macro

[Anton Staaf]

On Thu, Oct 13, 2011 at 11:15 AM, Mike Frysinger <vapier@gentoo.org> wrote:
> On Thursday 13 October 2011 14:06:41 Anton Staaf wrote:
>> On Wed, Oct 12, 2011 at 5:55 PM, Mike Frysinger wrote:
>> > On Wednesday 12 October 2011 19:55:59 Anton Staaf wrote:
>> >> ?doc/README.arm-caches | ? ?2 +
>> >
>> > seems like most of the advice in this is arch independent
>>
>> Agreed. ?It probably makes sense to change the name of the file. ?I'm not
>> sure that any of it's contents should be ARM specific moving forward. ?That
>> is, it reflects where all of the supported architectures should go yes?
>
> hmm, i thought you were adding this file, not updating it

Nope, just adding a line about the new buffer allocation macro.

> the enable_caches() part is ARM specific, as is the Cleanup Before Linux. ?but
> the rest should be in like README.caches.

Let's do that in a separate patch.

Thanks,
    Anton

> -mike
>

[U-Boot] [PATCH v3 0/6] Add cache line alignment support

[Anton Staaf]

On Wed, Oct 12, 2011 at 4:55 PM, Anton Staaf <robotboy@chromium.org> wrote:
> The cache line alignment issue has gone around a couple of times now. ?This
> patch set implements all of the details that we have discussed about the
> implementation of ALLOC_CACHE_ALIGN_BUFFER. ?It also includes patches that use
> the macro to fix MMC and ext2 buffers, as well as define the
> CONFIG_SYS_CACHELINE_SIZE value for Tegra.
>
> This series now depends on the series to add ARCH_DMA_MINALIGN for all
> architectures and must be applied after that series.
>
> This has been tested on a Seaboard.

This patch set has now been tested with MAKEALL for ARMv7a and
PowerPC.  It still
applies cleanly to TOT.  Should I resend or is it good as is?

Thanks,
    Anton

> Thanks,
> ? ?Anton
>
> ---
>
> Changes for v2:
> - Add comment describing why we are setting a default cacheline size
> - Remove Gerrit generated Change-Id: tags from commit messages
> - Add additional buffer alignments for mmc and part_efi code
>
> Changes for v3:
> - Don't set a default value for CONFIG_SYS_CACHELINE_SIZE
> - Use ARCH_DMA_MINALIGN to align DMA buffers
>
> Anton Staaf (6):
> ?cache: add ALLOC_CACHE_ALIGN_BUFFER macro
> ?tegra: define CONFIG_SYS_CACHELINE_SIZE for tegra
> ?mmc: dcache: allocate cache aligned buffer for scr and switch_status
> ?ext2: Cache line aligned partial sector bounce buffer
> ?mmc: dcache: allocate cache aligned buffers for ext_csd
> ?part_efi: dcache: allocate cacheline aligned buffers
>
> ?disk/part_efi.c ? ? ? ? ? ? ? ? | ? 18 ++++++------
> ?doc/README.arm-caches ? ? ? ? ? | ? ?2 +
> ?drivers/mmc/mmc.c ? ? ? ? ? ? ? | ? 14 +++++-----
> ?fs/ext2/dev.c ? ? ? ? ? ? ? ? ? | ? ?2 +-
> ?include/common.h ? ? ? ? ? ? ? ?| ? 58 +++++++++++++++++++++++++++++++++++++++
> ?include/configs/tegra2-common.h | ? ?2 +
> ?6 files changed, 79 insertions(+), 17 deletions(-)
>
> --
> 1.7.3.1
>
>

[U-Boot] [PATCH v3 1/6] cache: add ALLOC_CACHE_ALIGN_BUFFER macro

[Wolfgang Denk]

Dear Anton Staaf,

In message <1318463764-28244-2-git-send-email-robotboy@chromium.org> you wrote:
> This macro is used to allocate cache line size aligned stack
> buffers for use with DMA hardware.
> 
> Signed-off-by: Anton Staaf <robotboy@chromium.org>
> Cc: Lukasz Majewski <l.majewski@samsung.com>
> Cc: Kyungmin Park <kyungmin.park@samsung.com>
> Cc: Mike Frysinger <vapier@gentoo.org>
> Cc: Aneesh V <aneesh@ti.com>
> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
> Cc: Wolfgang Denk <wd@denx.de>
> ---
>  doc/README.arm-caches |    2 +
>  include/common.h      |   58 +++++++++++++++++++++++++++++++++++++++++++++++++
>  2 files changed, 60 insertions(+), 0 deletions(-)

Applied, thanks.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
                  Nail here --X-- for new monitor.

[U-Boot] [PATCH v3 2/6] tegra: define CONFIG_SYS_CACHELINE_SIZE for tegra

[Wolfgang Denk]

Dear Anton Staaf,

In message <1318463764-28244-3-git-send-email-robotboy@chromium.org> you wrote:
> Signed-off-by: Anton Staaf <robotboy@chromium.org>
> Cc: Tom Warren <twarren.nvidia@gmail.com>
> Cc: Simon Glass <sjg@chromium.org>
> Cc: Mike Frysinger <vapier@gentoo.org>
> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
> ---
>  include/configs/tegra2-common.h |    2 ++
>  1 files changed, 2 insertions(+), 0 deletions(-)

Applied, thanks.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
It's certainly  convenient  the  way  the  crime  (or  condition)  of
stupidity   carries   with   it  its  own  punishment,  automatically
admisistered without remorse, pity, or prejudice. :-)
         -- Tom Christiansen in <559seq$ag1$1@csnews.cs.colorado.edu>

[U-Boot] [PATCH v3 3/6] mmc: dcache: allocate cache aligned buffer for scr and switch_status

[Wolfgang Denk]

Dear Anton Staaf,

In message <1318463764-28244-4-git-send-email-robotboy@chromium.org> you wrote:
> Currently the sd_change_freq function allocates two buffers on the
> stack that it passes down to the MMC device driver.  These buffers
> could be unaligned to the L1 dcache line size.  This causes problems
> when using DMA and with caches enabled.
> 
> This patch correctly cache alignes the buffers used for reading the
> scr register and switch status values from an MMC device.
> 
> Signed-off-by: Anton Staaf <robotboy@chromium.org>
> Acked-by: Mike Frysinger <vapier@gentoo.org>
> Cc: Lukasz Majewski <l.majewski@samsung.com>
> Cc: Mike Frysinger <vapier@gentoo.org>
> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
> ---
>  drivers/mmc/mmc.c |   10 +++++-----
>  1 files changed, 5 insertions(+), 5 deletions(-)

Applied, thanks.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
If today is the first day of the rest of your life, what the hell was
yesterday?

[U-Boot] [PATCH v3 4/6] ext2: Cache line aligned partial sector bounce buffer

[Wolfgang Denk]

Dear Anton Staaf,

In message <1318463764-28244-5-git-send-email-robotboy@chromium.org> you wrote:
> Currently, if a device read request is done that does not begin or end
> on a sector boundary a stack allocated bounce buffer is used to perform
> the read, and then just the part of the sector that is needed is copied
> into the users buffer.  This stack allocation can mean that the bounce
> buffer will not be aligned to the dcache line size.  This is a problem
> when caches are enabled because unaligned cache invalidates are not
> safe.
> 
> This patch uses ALLOC_CACHE_ALIGN_BUFFER to create a stack allocated
> cache line size aligned bounce buffer.
> 
> Signed-off-by: Anton Staaf <robotboy@chromium.org>
> Acked-by: Mike Frysinger <vapier@gentoo.org>
> Cc: Lukasz Majewski <l.majewski@samsung.com>
> Cc: Mike Frysinger <vapier@gentoo.org>
> Cc: Dave Liu <r63238@freescale.com>
> Cc: Andy Fleming <afleming@gmail.com>
> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
> ---
>  fs/ext2/dev.c |    2 +-
>  1 files changed, 1 insertions(+), 1 deletions(-)

Applied, thanks.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
If something is different, it's either better or worse,  and  usually
both.                                                    - Larry Wall

[U-Boot] [PATCH v3 5/6] mmc: dcache: allocate cache aligned buffers for ext_csd

[Wolfgang Denk]

Dear Anton Staaf,

In message <1318463764-28244-6-git-send-email-robotboy@chromium.org> you wrote:
> Currently the mmc_change_freq and mmc_startup functions allocates
> buffers on the stack that are passed down to the MMC device driver.
> These buffers could be unaligned to the L1 dcache line size.  This
> causes problems when using DMA and with caches enabled.
> 
> This patch correctly cache alignes the buffers used for reading the
> ext_csd data from an MMC device.
> 
> Signed-off-by: Anton Staaf <robotboy@chromium.org>
> Cc: Lukasz Majewski <l.majewski@samsung.com>
> Cc: Mike Frysinger <vapier@gentoo.org>
> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
> ---
>  drivers/mmc/mmc.c |    4 ++--
>  1 files changed, 2 insertions(+), 2 deletions(-)

Applied, thanks.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
HEALTH WARNING: Care Should Be Taken When Lifting This Product, Since
Its Mass, and Thus Its Weight, Is Dependent on Its Velocity  Relative
to the User.

[U-Boot] [PATCH v3 6/6] part_efi: dcache: allocate cacheline aligned buffers

[Wolfgang Denk]

Dear Anton Staaf,

In message <1318463764-28244-7-git-send-email-robotboy@chromium.org> you wrote:
> Currently part_efi.c allocates buffers for the gpt_header, the
> legacy_mbr, and the pte (partition table entry) that may be
> incorrectly aligned for DMA operations.
> 
> This patch uses ALLOC_CACHE_ALIGN_BUFFER for the stack allocated
> buffers and memalign to replace the malloc of the pte.
> 
> Signed-off-by: Anton Staaf <robotboy@chromium.org>
> Cc: Lukasz Majewski <l.majewski@samsung.com>
> Cc: Mike Frysinger <vapier@gentoo.org>
> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
> ---
>  disk/part_efi.c |   18 +++++++++---------
>  1 files changed, 9 insertions(+), 9 deletions(-)

Applied, thanks.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
In the strict scientific sense we all feed on death -- even
vegetarians.
	-- Spock, "Wolf in the Fold", stardate 3615.4

[U-Boot] [PATCH v3 0/6] Add cache line alignment support

[Wolfgang Denk]

Dear Anton Staaf,

In message <CAF6FioXXXr8tn5Os8WeRM5k+5S1PVD7zVKLJQEy3SoLUbu_ZwA@mail.gmail.com> you wrote:
>
> This patch set has now been tested with MAKEALL for ARMv7a and
> PowerPC.  It still
> applies cleanly to TOT.  Should I resend or is it good as is?

No need to resend.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
HR Manager to job candidate "I see you've had no  computer  training.
Although  that  qualifies  you  for upper management, it means you're
under-qualified for our entry level positions."