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From: Joerg Roedel <joerg.roedel-5C7GfCeVMHo@public.gmane.org>
To: Hiroshi Doyu <hdoyu-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
Cc: "joro-zLv9SwRftAIdnm+yROfE0A@public.gmane.org"
	<joro-zLv9SwRftAIdnm+yROfE0A@public.gmane.org>,
	"linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org"
	<linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
	"linaro-mm-sig-bounces-cunTk1MwBs8s++Sfvej+rw@public.gmane.org"
	<linaro-mm-sig-bounces-cunTk1MwBs8s++Sfvej+rw@public.gmane.org>,
	"iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org"
	<iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org>,
	"linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org"
	<linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
	"linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org"
	<linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org>
Subject: Re: [PATCH 2/2] ARM: IOMMU: Tegra30: Add iommu_ops for SMMU driver
Date: Tue, 24 Jan 2012 12:04:44 +0100	[thread overview]
Message-ID: <20120124110444.GB19255@amd.com> (raw)
In-Reply-To: <20120124.115701.2179509760878976509.hdoyu-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

On Tue, Jan 24, 2012 at 10:57:01AM +0100, Hiroshi Doyu wrote:
> > Why do you completly ignore the size parameter in this function (and
> > in the unmap part below)?
> > According to the page-sizes you export to the generic layer size can be
> > 4k or 4M. You need to take care of that in this function.
> 
> I'll drop 4MB support here once. I'll make another patch for 4MB page
> support later.

Okay, so when you only export 4k everything should be fine.

> > Hmm, this looks like there is a 1-1 mapping between hardware SMMU
> > devices and domains. This is not consistent with IOMMU-API semantics
> > where a domain can contain devices behind different SMMUs. Please fix
> > that.
> 
> I'm a bit confused with the concept of "domain". I thought that
> "domain" is equivalent to a "virtual address space". Usually a IOMMU
> device provides a virtual address space for multiple client
> devices. IOW, a IOMMU device provides a virtual address space, which
> can be shared with multiple client devices.
> 
> Actually Tegra SMMU case, a single IOMMU device has 4 different
> virtual address speace("smmu_as"). Each "smmu_as" has its own virtual
> address space. "smmu_as[i]" has mutiple "smmu_client" devices.
> 
>   smmu_as[i] == domain[i]
> 
> I don't understand why "a domain can contain devices behind different
> SMMUs" because those client devices belong to different virtual
> address spaces, and they should belong to different "domains".
> 
> Could you please explain a bit more about "domain"?

A domain is, as you said, a virtual address space for IO devices. But
the important point is, an arbitrary number of devices can be part of a
domain. This also means that the devices can be behind different
hardware SMMUs. In this case your driver needs to program the page-table
pointer into more than one SMMU to give devices behind different SMMUs
the same address space.


	Joerg

-- 
AMD Operating System Research Center

Advanced Micro Devices GmbH Einsteinring 24 85609 Dornach
General Managers: Alberto Bozzo
Registration: Dornach, Landkr. Muenchen; Registerger. Muenchen, HRB Nr. 43632

WARNING: multiple messages have this Message-ID (diff)
From: joerg.roedel@amd.com (Joerg Roedel)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 2/2] ARM: IOMMU: Tegra30: Add iommu_ops for SMMU driver
Date: Tue, 24 Jan 2012 12:04:44 +0100	[thread overview]
Message-ID: <20120124110444.GB19255@amd.com> (raw)
In-Reply-To: <20120124.115701.2179509760878976509.hdoyu@nvidia.com>

On Tue, Jan 24, 2012 at 10:57:01AM +0100, Hiroshi Doyu wrote:
> > Why do you completly ignore the size parameter in this function (and
> > in the unmap part below)?
> > According to the page-sizes you export to the generic layer size can be
> > 4k or 4M. You need to take care of that in this function.
> 
> I'll drop 4MB support here once. I'll make another patch for 4MB page
> support later.

Okay, so when you only export 4k everything should be fine.

> > Hmm, this looks like there is a 1-1 mapping between hardware SMMU
> > devices and domains. This is not consistent with IOMMU-API semantics
> > where a domain can contain devices behind different SMMUs. Please fix
> > that.
> 
> I'm a bit confused with the concept of "domain". I thought that
> "domain" is equivalent to a "virtual address space". Usually a IOMMU
> device provides a virtual address space for multiple client
> devices. IOW, a IOMMU device provides a virtual address space, which
> can be shared with multiple client devices.
> 
> Actually Tegra SMMU case, a single IOMMU device has 4 different
> virtual address speace("smmu_as"). Each "smmu_as" has its own virtual
> address space. "smmu_as[i]" has mutiple "smmu_client" devices.
> 
>   smmu_as[i] == domain[i]
> 
> I don't understand why "a domain can contain devices behind different
> SMMUs" because those client devices belong to different virtual
> address spaces, and they should belong to different "domains".
> 
> Could you please explain a bit more about "domain"?

A domain is, as you said, a virtual address space for IO devices. But
the important point is, an arbitrary number of devices can be part of a
domain. This also means that the devices can be behind different
hardware SMMUs. In this case your driver needs to program the page-table
pointer into more than one SMMU to give devices behind different SMMUs
the same address space.


	Joerg

-- 
AMD Operating System Research Center

Advanced Micro Devices GmbH Einsteinring 24 85609 Dornach
General Managers: Alberto Bozzo
Registration: Dornach, Landkr. Muenchen; Registerger. Muenchen, HRB Nr. 43632

WARNING: multiple messages have this Message-ID (diff)
From: Joerg Roedel <joerg.roedel@amd.com>
To: Hiroshi Doyu <hdoyu@nvidia.com>
Cc: "joro@8bytes.org" <joro@8bytes.org>,
	"linux-tegra@vger.kernel.org" <linux-tegra@vger.kernel.org>,
	"linaro-mm-sig-bounces@lists.linaro.org" 
	<linaro-mm-sig-bounces@lists.linaro.org>,
	"iommu@lists.linux-foundation.org"
	<iommu@lists.linux-foundation.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"linux-arm-kernel@lists.infradead.org" 
	<linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH 2/2] ARM: IOMMU: Tegra30: Add iommu_ops for SMMU driver
Date: Tue, 24 Jan 2012 12:04:44 +0100	[thread overview]
Message-ID: <20120124110444.GB19255@amd.com> (raw)
In-Reply-To: <20120124.115701.2179509760878976509.hdoyu@nvidia.com>

On Tue, Jan 24, 2012 at 10:57:01AM +0100, Hiroshi Doyu wrote:
> > Why do you completly ignore the size parameter in this function (and
> > in the unmap part below)?
> > According to the page-sizes you export to the generic layer size can be
> > 4k or 4M. You need to take care of that in this function.
> 
> I'll drop 4MB support here once. I'll make another patch for 4MB page
> support later.

Okay, so when you only export 4k everything should be fine.

> > Hmm, this looks like there is a 1-1 mapping between hardware SMMU
> > devices and domains. This is not consistent with IOMMU-API semantics
> > where a domain can contain devices behind different SMMUs. Please fix
> > that.
> 
> I'm a bit confused with the concept of "domain". I thought that
> "domain" is equivalent to a "virtual address space". Usually a IOMMU
> device provides a virtual address space for multiple client
> devices. IOW, a IOMMU device provides a virtual address space, which
> can be shared with multiple client devices.
> 
> Actually Tegra SMMU case, a single IOMMU device has 4 different
> virtual address speace("smmu_as"). Each "smmu_as" has its own virtual
> address space. "smmu_as[i]" has mutiple "smmu_client" devices.
> 
>   smmu_as[i] == domain[i]
> 
> I don't understand why "a domain can contain devices behind different
> SMMUs" because those client devices belong to different virtual
> address spaces, and they should belong to different "domains".
> 
> Could you please explain a bit more about "domain"?

A domain is, as you said, a virtual address space for IO devices. But
the important point is, an arbitrary number of devices can be part of a
domain. This also means that the devices can be behind different
hardware SMMUs. In this case your driver needs to program the page-table
pointer into more than one SMMU to give devices behind different SMMUs
the same address space.


	Joerg

-- 
AMD Operating System Research Center

Advanced Micro Devices GmbH Einsteinring 24 85609 Dornach
General Managers: Alberto Bozzo
Registration: Dornach, Landkr. Muenchen; Registerger. Muenchen, HRB Nr. 43632


  parent reply	other threads:[~2012-01-24 11:04 UTC|newest]

Thread overview: 71+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2012-01-05  7:11 [PATCH v3 0/2] ARM: IOMMU: tegra: Add iommu_ops for GART/SMMU driver Hiroshi DOYU
2012-01-05  7:11 ` Hiroshi DOYU
2012-01-05  7:11 ` Hiroshi DOYU
2012-01-05  7:11 ` [PATCH 1/2] ARM: IOMMU: Tegra20: Add iommu_ops for GART driver Hiroshi DOYU
2012-01-05  7:11   ` Hiroshi DOYU
     [not found]   ` <1325747509-29665-2-git-send-email-hdoyu-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2012-01-23 15:00     ` Joerg Roedel
2012-01-23 15:00       ` Joerg Roedel
2012-01-23 15:00       ` Joerg Roedel
     [not found]       ` <20120123150048.GB6269-zLv9SwRftAIdnm+yROfE0A@public.gmane.org>
2012-01-25  7:40         ` Hiroshi Doyu
2012-01-25  7:40           ` Hiroshi Doyu
2012-01-25  7:40           ` Hiroshi Doyu
     [not found]           ` <20120125.094020.983282777619146490.hdoyu-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2012-01-26 11:58             ` joro-zLv9SwRftAIdnm+yROfE0A
2012-01-26 11:58               ` joro
2012-01-26 11:58               ` joro at 8bytes.org
     [not found]               ` <20120126115813.GF6269-zLv9SwRftAIdnm+yROfE0A@public.gmane.org>
2012-01-26 14:45                 ` Hiroshi Doyu
2012-01-26 14:45                   ` Hiroshi Doyu
2012-01-26 14:45                   ` Hiroshi Doyu
2012-01-05  7:11 ` [PATCH 2/2] ARM: IOMMU: Tegra30: Add iommu_ops for SMMU driver Hiroshi DOYU
2012-01-05  7:11   ` Hiroshi DOYU
     [not found]   ` <1325747509-29665-3-git-send-email-hdoyu-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2012-01-23 15:43     ` Joerg Roedel
2012-01-23 15:43       ` Joerg Roedel
2012-01-23 15:43       ` Joerg Roedel
     [not found]       ` <20120123154310.GC6269-zLv9SwRftAIdnm+yROfE0A@public.gmane.org>
2012-01-24  9:57         ` Hiroshi Doyu
2012-01-24  9:57           ` Hiroshi Doyu
2012-01-24  9:57           ` Hiroshi Doyu
     [not found]           ` <20120124.115701.2179509760878976509.hdoyu-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2012-01-24 11:04             ` Joerg Roedel [this message]
2012-01-24 11:04               ` Joerg Roedel
2012-01-24 11:04               ` Joerg Roedel
     [not found]               ` <20120124110444.GB19255-5C7GfCeVMHo@public.gmane.org>
2012-01-24 11:36                 ` Hiroshi Doyu
2012-01-24 11:36                   ` Hiroshi Doyu
2012-01-24 11:36                   ` Hiroshi Doyu
     [not found]                   ` <20120124.133614.1646093482547685131.hdoyu-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2012-01-24 11:57                     ` joerg.roedel-5C7GfCeVMHo
2012-01-24 11:57                       ` joerg.roedel
2012-01-24 11:57                       ` joerg.roedel at amd.com
     [not found]                       ` <20120124115723.GC19255-5C7GfCeVMHo@public.gmane.org>
2012-01-24 12:07                         ` Hiroshi Doyu
2012-01-24 12:07                           ` Hiroshi Doyu
2012-01-24 12:07                           ` Hiroshi Doyu
2012-01-24 13:41         ` Hiroshi Doyu
2012-01-24 13:41           ` Hiroshi Doyu
2012-01-24 13:41           ` Hiroshi Doyu
     [not found]           ` <20120124.154121.1062920821192552748.hdoyu-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2012-01-24 13:46             ` Felipe Balbi
2012-01-24 13:46               ` Felipe Balbi
2012-01-24 13:46               ` Felipe Balbi
     [not found]               ` <20120124134601.GT27414-UiBtZHVXSwEVvW8u9ZQWYwjfymiNCTlR@public.gmane.org>
2012-01-24 14:25                 ` joro-zLv9SwRftAIdnm+yROfE0A
2012-01-24 14:25                   ` joro
2012-01-24 14:25                   ` joro at 8bytes.org
     [not found]                   ` <20120124142521.GE6269-zLv9SwRftAIdnm+yROfE0A@public.gmane.org>
2012-01-25  7:39                     ` Hiroshi Doyu
2012-01-25  7:39                       ` Hiroshi Doyu
2012-01-25  7:39                       ` Hiroshi Doyu
     [not found]                       ` <20120125.093932.783007031082378997.hdoyu-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2012-01-26 14:59                         ` joro-zLv9SwRftAIdnm+yROfE0A
2012-01-26 14:59                           ` joro
2012-01-26 14:59                           ` joro at 8bytes.org
     [not found] ` <1325747509-29665-1-git-send-email-hdoyu-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2012-01-05  7:17   ` [PATCH v3 0/2] ARM: IOMMU: tegra: Add iommu_ops for GART/SMMU driver Hiroshi Doyu
2012-01-05  7:17     ` Hiroshi Doyu
2012-01-05  7:17     ` Hiroshi Doyu
     [not found]     ` <20120105091718.3fb378b2a1d390f9dd63c396-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2012-01-05 12:53       ` Russell King - ARM Linux
2012-01-05 12:53         ` Russell King - ARM Linux
2012-01-05 12:53         ` Russell King - ARM Linux
     [not found]         ` <20120105125326.GT11810-l+eeeJia6m9vn6HldHNs0ANdhmdF6hFW@public.gmane.org>
2012-01-05 14:29           ` Hiroshi Doyu
2012-01-05 14:29             ` Hiroshi Doyu
2012-01-05 14:29             ` Hiroshi Doyu
     [not found]             ` <20120105.162930.604365154868332443.hdoyu-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2012-01-05 14:46               ` Russell King - ARM Linux
2012-01-05 14:46                 ` Russell King - ARM Linux
2012-01-05 14:46                 ` Russell King - ARM Linux
     [not found]                 ` <20120105144631.GV11810-l+eeeJia6m9vn6HldHNs0ANdhmdF6hFW@public.gmane.org>
2012-01-11 14:24                   ` Hiroshi Doyu
2012-01-11 14:24                     ` Hiroshi Doyu
2012-01-11 14:24                     ` Hiroshi Doyu
2012-01-09  0:39         ` KyongHo Cho
2012-01-09  0:39           ` KyongHo Cho
2012-01-09 11:45           ` Russell King - ARM Linux
2012-01-09 11:45             ` Russell King - ARM Linux

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