* [PATCH] ASoC: tlv320aic3x: add input clock selection
@ 2012-07-10 12:36 Jiri Prchal
2012-07-10 13:42 ` Mark Brown
0 siblings, 1 reply; 5+ messages in thread
From: Jiri Prchal @ 2012-07-10 12:36 UTC (permalink / raw)
To: broonie, alsa-devel; +Cc: Jiri Prchal
This patch adds input selection of main codec clock - from what pin.
Both registers set same value since codec uses clock divider or pll at one time.
Signed-off-by: Jiri Prchal <jiri.prchal@aksignal.cz>
---
sound/soc/codecs/tlv320aic3x.c | 6 ++++++
sound/soc/codecs/tlv320aic3x.h | 8 ++++++++
2 files changed, 14 insertions(+), 0 deletions(-)
diff --git a/sound/soc/codecs/tlv320aic3x.c b/sound/soc/codecs/tlv320aic3x.c
index 11e195f..5bc5543 100644
--- a/sound/soc/codecs/tlv320aic3x.c
+++ b/sound/soc/codecs/tlv320aic3x.c
@@ -1030,6 +1030,12 @@ static int aic3x_set_dai_sysclk(struct snd_soc_dai *codec_dai,
struct snd_soc_codec *codec = codec_dai->codec;
struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
+ /* set clock on MCLK or GPIO2 or BCLK */
+ snd_soc_update_bits(codec, AIC3X_CLKGEN_CTRL_REG, PLLCLK_IN_MASK,
+ clk_id << PLLCLK_IN_SHIFT);
+ snd_soc_update_bits(codec, AIC3X_CLKGEN_CTRL_REG, CLKDIV_IN_MASK,
+ clk_id << CLKDIV_IN_SHIFT);
+
aic3x->sysclk = freq;
return 0;
}
diff --git a/sound/soc/codecs/tlv320aic3x.h b/sound/soc/codecs/tlv320aic3x.h
index 586c5d5..ed4a788 100644
--- a/sound/soc/codecs/tlv320aic3x.h
+++ b/sound/soc/codecs/tlv320aic3x.h
@@ -195,6 +195,14 @@
#define PLL_CLKIN_SHIFT 4
#define MCLK_SOURCE 0x0
#define PLL_CLKDIV_SHIFT 0
+#define PLLCLK_IN_MASK 0x30
+#define PLLCLK_IN_SHIFT 4
+#define CLKDIV_IN_MASK 0xc0
+#define CLKDIV_IN_SHIFT 6
+/* clock in source */
+#define CLKIN_MCLK 0
+#define CLKIN_GPIO2 1
+#define CLKIN_BCLK 2
/* Software reset register bits */
#define SOFT_RESET 0x80
--
1.7.7
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH] ASoC: tlv320aic3x: add input clock selection
@ 2012-06-26 10:21 Prchal Jiří
2012-06-26 10:26 ` Mark Brown
0 siblings, 1 reply; 5+ messages in thread
From: Prchal Jiří @ 2012-06-26 10:21 UTC (permalink / raw)
To: alsa-devel, vbarinov, mr.swami.reddy, peter.ujfalusi, Mark Brown,
sudhakar.raj, nsekhar, lrg
This patch adds input selection of main codec clock - from what pin.
Tested with TLV320AIC3106 on BCLK and MCLK.
Signed-off-by: Jiri Prchal <jiri.prchal@aksignal.cz>
--- /home/prchal/arm/fw-cdu/linux/linux-3.5-rc3/sound/soc/codecs/tlv320aic3x.c.orig
+++ /home/prchal/arm/fw-cdu/linux/linux-3.5-rc3/sound/soc/codecs/tlv320aic3x.c
@@ -972,6 +972,10 @@
struct snd_soc_codec *codec = codec_dai->codec;
struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
+ /* set clock on MCLK or GPIO2 or BCLK */
+ snd_soc_update_bits(codec, AIC3X_CLKGEN_CTRL_REG, PLLCLK_IN_MASK, clk_id);
+ snd_soc_update_bits(codec, AIC3X_CLKGEN_CTRL_REG, CLKDIV_IN_MASK, clk_id);
+
aic3x->sysclk = freq;
return 0;
}
--- /home/prchal/arm/fw-cdu/linux/linux-3.5-rc3/sound/soc/codecs/tlv320aic3x.h.orig
+++ /home/prchal/arm/fw-cdu/linux/linux-3.5-rc3/sound/soc/codecs/tlv320aic3x.h
@@ -178,6 +178,13 @@
#define PLL_CLKIN_SHIFT 4
#define MCLK_SOURCE 0x0
#define PLL_CLKDIV_SHIFT 0
+#define PLLCLK_IN_MASK 0x30
+#define CLKDIV_IN_MASK 0xc0
+/* clock in source */
+#define CLKIN_MCLK 0
+#define CLKIN_GPIO2 1
+#define CLKIN_BCLK 2
+
/* Software reset register bits */
#define SOFT_RESET 0x80
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] ASoC: tlv320aic3x: add input clock selection
2012-06-26 10:21 Prchal Jiří
@ 2012-06-26 10:26 ` Mark Brown
2012-06-26 11:47 ` Prchal Jiří
0 siblings, 1 reply; 5+ messages in thread
From: Mark Brown @ 2012-06-26 10:26 UTC (permalink / raw)
To: Prchal Jiří
Cc: vbarinov, alsa-devel, sudhakar.raj, nsekhar, peter.ujfalusi,
mr.swami.reddy, lrg
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On Tue, Jun 26, 2012 at 12:21:28PM +0200, Prchal Jiří wrote:
> + /* set clock on MCLK or GPIO2 or BCLK */
> + snd_soc_update_bits(codec, AIC3X_CLKGEN_CTRL_REG, PLLCLK_IN_MASK, clk_id);
> + snd_soc_update_bits(codec, AIC3X_CLKGEN_CTRL_REG, CLKDIV_IN_MASK, clk_id);
Normally it's possible to set these separately. Is there a reason why
they have to be the same (and if so why has the chip got separate
registers)?
> +#define PLLCLK_IN_MASK 0x30
> +#define CLKDIV_IN_MASK 0xc0
> +/* clock in source */
> +#define CLKIN_MCLK 0
> +#define CLKIN_GPIO2 1
> +#define CLKIN_BCLK 2
This doesn't look right - you use the clock source values directly above
but they need shifting to be used as if they're used directly they'll
always come out as zero. It'd also be better to have some bounds
checking on the values.
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^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] ASoC: tlv320aic3x: add input clock selection
2012-06-26 10:26 ` Mark Brown
@ 2012-06-26 11:47 ` Prchal Jiří
0 siblings, 0 replies; 5+ messages in thread
From: Prchal Jiří @ 2012-06-26 11:47 UTC (permalink / raw)
To: Mark Brown
Cc: vbarinov, alsa-devel, sudhakar.raj, nsekhar, peter.ujfalusi,
mr.swami.reddy, lrg
Hi Mark,
Dne 26.6.2012 12:26, Mark Brown napsal(a):
> On Tue, Jun 26, 2012 at 12:21:28PM +0200, Prchal Jiří wrote:
>
>> + /* set clock on MCLK or GPIO2 or BCLK */
>> + snd_soc_update_bits(codec, AIC3X_CLKGEN_CTRL_REG, PLLCLK_IN_MASK, clk_id);
>> + snd_soc_update_bits(codec, AIC3X_CLKGEN_CTRL_REG, CLKDIV_IN_MASK, clk_id);
>
> Normally it's possible to set these separately. Is there a reason why
> they have to be the same (and if so why has the chip got separate
> registers)?
It could be set separately but in my opinion that doesn't make sense. Codec has one inner clock which is from divider or
pll. In one time is used only one clock source so it doesn't matter how is set the other. And the other must be set to
someone, cannot be switched off.
Normally board design contain one clock connected to one of tree input pins. This is to select pin.
Selection of input divider or pll is done somewhere else depended on frequency and sampling rate.
Can someone from TI approve or disapprove this?
>
>> +#define PLLCLK_IN_MASK 0x30
>> +#define CLKDIV_IN_MASK 0xc0
>> +/* clock in source */
>> +#define CLKIN_MCLK 0
>> +#define CLKIN_GPIO2 1
>> +#define CLKIN_BCLK 2
>
> This doesn't look right - you use the clock source values directly above
> but they need shifting to be used as if they're used directly they'll
> always come out as zero. It'd also be better to have some bounds
> checking on the values.
You are right, my mistake. Below is corrected patch.
Thanks.
--- /home/prchal/arm/fw-cdu/linux/linux-3.5-rc3/sound/soc/codecs/tlv320aic3x.c.orig
+++ /home/prchal/arm/fw-cdu/linux/linux-3.5-rc3/sound/soc/codecs/tlv320aic3x.c
@@ -972,6 +972,12 @@
struct snd_soc_codec *codec = codec_dai->codec;
struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
+ /* set clock on MCLK or GPIO2 or BCLK */
+ snd_soc_update_bits(codec, AIC3X_CLKGEN_CTRL_REG, PLLCLK_IN_MASK,
+ clk_id << PLLCLK_IN_SHIFT);
+ snd_soc_update_bits(codec, AIC3X_CLKGEN_CTRL_REG, CLKDIV_IN_MASK,
+ clk_id << CLKDIV_IN_SHIFT);
+
aic3x->sysclk = freq;
return 0;
}
--- /home/prchal/arm/fw-cdu/linux/linux-3.5-rc3/sound/soc/codecs/tlv320aic3x.h.orig
+++ /home/prchal/arm/fw-cdu/linux/linux-3.5-rc3/sound/soc/codecs/tlv320aic3x.h
@@ -178,6 +178,15 @@
#define PLL_CLKIN_SHIFT 4
#define MCLK_SOURCE 0x0
#define PLL_CLKDIV_SHIFT 0
+#define PLLCLK_IN_MASK 0x30
+#define PLLCLK_IN_SHIFT 4
+#define CLKDIV_IN_MASK 0xc0
+#define CLKDIV_IN_SHIFT 6
+/* clock in source */
+#define CLKIN_MCLK 0
+#define CLKIN_GPIO2 1
+#define CLKIN_BCLK 2
+
/* Software reset register bits */
#define SOFT_RESET 0x80
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2012-07-10 12:36 [PATCH] ASoC: tlv320aic3x: add input clock selection Jiri Prchal
2012-07-10 13:42 ` Mark Brown
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2012-06-26 10:21 Prchal Jiří
2012-06-26 10:26 ` Mark Brown
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