From: Jesse Barnes <jbarnes@virtuousgeek.org>
To: Daniel Vetter <daniel@ffwll.ch>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 4/9] drm/i915: add post-flush store dw workaround
Date: Tue, 25 Sep 2012 04:07:04 -0700 [thread overview]
Message-ID: <20120925040704.46bf38fa@jbarnes-desktop> (raw)
In-Reply-To: <20120925084928.GE3824@bremse>
On Tue, 25 Sep 2012 10:49:28 +0200
Daniel Vetter <daniel@ffwll.ch> wrote:
> On Wed, Sep 19, 2012 at 01:28:58PM -0700, Jesse Barnes wrote:
> > Several platforms need this to flush the CS write buffers.
>
> Chris spent quite some effort to dump less crap into the rings on gen6,
> and your description here sounds like we only need this when flushing
> write caches. Or it might only apply to CS writes (in which case this is
> at the wrong spot). In any case, can you please double check where exactly
> we need this and only add it there, with a neat comment explaining things
> added?
"write caches" as in "any time we do a store dw and want to read the
result coherently" is my understanding.
> I'm bitching because afair the CS stuff the windows driver emits (of which
> I've seen some traces) only emits one such 8x MI_WRITE block per batch,
> whereas your code here would emit 2 such 2x MI_WRITE blocks.
Doing it once should be sufficient, I guess I need to split this out
(probably a good idea anyway for comment & naming purposes).
--
Jesse Barnes, Intel Open Source Technology Center
next prev parent reply other threads:[~2012-09-25 11:06 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-09-19 20:28 [PATCH 1/9] drm/i915: disable DOP clock gating on VLV and IVB Jesse Barnes
2012-09-19 20:28 ` [PATCH 2/9] drm/i915: implement WaForceL3Serialization " Jesse Barnes
2012-09-19 20:28 ` [PATCH 3/9] drm/i915: add a HSW scratch location for flush commands Jesse Barnes
2012-09-25 8:54 ` Daniel Vetter
2012-09-25 11:08 ` Jesse Barnes
2012-09-25 11:47 ` Daniel Vetter
2012-09-25 12:08 ` Jesse Barnes
2012-09-19 20:28 ` [PATCH 4/9] drm/i915: add post-flush store dw workaround Jesse Barnes
2012-09-25 8:49 ` Daniel Vetter
2012-09-25 11:07 ` Jesse Barnes [this message]
2012-09-19 20:28 ` [PATCH 5/9] drm/i915: implement WaDisableEarlyCull for VLV and IVB Jesse Barnes
2012-09-19 20:29 ` [PATCH 6/9] drm/i915: implement WaDisablePSDDualDispatchEnable on IVB and VLV Jesse Barnes
2012-09-25 8:51 ` Daniel Vetter
2012-10-01 16:52 ` Lespiau, Damien
2012-10-01 16:56 ` Jesse Barnes
2012-10-01 17:07 ` Lespiau, Damien
2012-10-01 16:57 ` Lespiau, Damien
2012-09-19 20:29 ` [PATCH 7/9] drm/i915: limit VLV IRQ enables to those we use Jesse Barnes
2012-09-26 14:16 ` Daniel Vetter
2012-09-19 20:29 ` [PATCH 8/9] drm/i915: TLB invalidation with MI_FLUSH_SW requires a post-sync op Jesse Barnes
2012-09-19 20:29 ` [PATCH 9/9] drm/i915: PIPE_CONTROL TLB invalidate requires CS stall Jesse Barnes
2012-09-19 21:41 ` [PATCH 1/9] drm/i915: disable DOP clock gating on VLV and IVB Ben Widawsky
2012-09-19 22:06 ` Jesse Barnes
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