From: Daniel Vetter <daniel@ffwll.ch>
To: Jesse Barnes <jbarnes@virtuousgeek.org>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 6/9] drm/i915: implement WaDisablePSDDualDispatchEnable on IVB and VLV
Date: Tue, 25 Sep 2012 10:51:32 +0200 [thread overview]
Message-ID: <20120925085132.GF3824@bremse> (raw)
In-Reply-To: <1348086543-24427-6-git-send-email-jbarnes@virtuousgeek.org>
On Wed, Sep 19, 2012 at 01:29:00PM -0700, Jesse Barnes wrote:
> Workaround for dual port PS dispatch on GT1.
>
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 4 ++++
> drivers/gpu/drm/i915/intel_pm.c | 16 ++++++++++++++++
> 2 files changed, 20 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index e570aea..e863973 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4249,6 +4249,10 @@
> #define GEN7_L3LOG_BASE 0xB070
> #define GEN7_L3LOG_SIZE 0x80
>
> +#define GEN7_HALF_SLICE_CHICKEN1 0xe100 /* IVB GT1 + VLV */
> +#define GEN7_HALF_SLICE_CHICKEN1_IVB 0xf100
> +#define GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE (1<<3)
> +
> #define G4X_AUD_VID_DID 0x62020
> #define INTEL_AUDIO_DEVCL 0x808629FB
> #define INTEL_AUDIO_DEVBLC 0x80862801
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 372a398..f860cdd 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3537,6 +3537,17 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
> CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
> CHICKEN3_DGMG_DONE_FIX_DISABLE);
>
> + /* WaDisablePSDDualDispatchEnable */
> + if (dev->pci_device == 0x0156 ||
> + dev->pci_device == 0x0152)
Can we please have a comment here explaining which pci ids we're matching
here? Just in case we add yet another variant sometime. Or just plainly
use IS_MOBILE, which seems to match here ...
-Daniel
> + I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
> + I915_READ(GEN7_HALF_SLICE_CHICKEN1) |
> + _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
> + else
> + I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_IVB,
> + I915_READ(GEN7_HALF_SLICE_CHICKEN1) |
> + _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
> +
> /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
> I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
> GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
> @@ -3618,6 +3629,11 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
> CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
> CHICKEN3_DGMG_DONE_FIX_DISABLE);
>
> + /* WaDisablePSDDualDispatchEnable */
> + I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
> + I915_READ(GEN7_HALF_SLICE_CHICKEN1) |
> + _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
> +
> /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
> I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
> GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
> --
> 1.7.9.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
next prev parent reply other threads:[~2012-09-25 8:51 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-09-19 20:28 [PATCH 1/9] drm/i915: disable DOP clock gating on VLV and IVB Jesse Barnes
2012-09-19 20:28 ` [PATCH 2/9] drm/i915: implement WaForceL3Serialization " Jesse Barnes
2012-09-19 20:28 ` [PATCH 3/9] drm/i915: add a HSW scratch location for flush commands Jesse Barnes
2012-09-25 8:54 ` Daniel Vetter
2012-09-25 11:08 ` Jesse Barnes
2012-09-25 11:47 ` Daniel Vetter
2012-09-25 12:08 ` Jesse Barnes
2012-09-19 20:28 ` [PATCH 4/9] drm/i915: add post-flush store dw workaround Jesse Barnes
2012-09-25 8:49 ` Daniel Vetter
2012-09-25 11:07 ` Jesse Barnes
2012-09-19 20:28 ` [PATCH 5/9] drm/i915: implement WaDisableEarlyCull for VLV and IVB Jesse Barnes
2012-09-19 20:29 ` [PATCH 6/9] drm/i915: implement WaDisablePSDDualDispatchEnable on IVB and VLV Jesse Barnes
2012-09-25 8:51 ` Daniel Vetter [this message]
2012-10-01 16:52 ` Lespiau, Damien
2012-10-01 16:56 ` Jesse Barnes
2012-10-01 17:07 ` Lespiau, Damien
2012-10-01 16:57 ` Lespiau, Damien
2012-09-19 20:29 ` [PATCH 7/9] drm/i915: limit VLV IRQ enables to those we use Jesse Barnes
2012-09-26 14:16 ` Daniel Vetter
2012-09-19 20:29 ` [PATCH 8/9] drm/i915: TLB invalidation with MI_FLUSH_SW requires a post-sync op Jesse Barnes
2012-09-19 20:29 ` [PATCH 9/9] drm/i915: PIPE_CONTROL TLB invalidate requires CS stall Jesse Barnes
2012-09-19 21:41 ` [PATCH 1/9] drm/i915: disable DOP clock gating on VLV and IVB Ben Widawsky
2012-09-19 22:06 ` Jesse Barnes
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