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From: Daniel Vetter <daniel@ffwll.ch>
To: Jesse Barnes <jbarnes@virtuousgeek.org>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 3/9] drm/i915: add a HSW scratch location for flush commands
Date: Tue, 25 Sep 2012 10:54:00 +0200	[thread overview]
Message-ID: <20120925085400.GG3824@bremse> (raw)
In-Reply-To: <1348086543-24427-3-git-send-email-jbarnes@virtuousgeek.org>

On Wed, Sep 19, 2012 at 01:28:57PM -0700, Jesse Barnes wrote:
> Some commands and workarounds require stores to occur to function
> correctly, so add some scratch space to the HWS page to accommodate
> them.
> 
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> ---
>  drivers/gpu/drm/i915/intel_ringbuffer.h |    1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
> index 2ea7a31..ef85742 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.h
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
> @@ -181,6 +181,7 @@ intel_read_status_page(struct intel_ring_buffer *ring,
>   * The area from dword 0x20 to 0x3ff is available for driver usage.
>   */
>  #define I915_GEM_HWS_INDEX		0x20
> +#define I915_GEM_SCRATCH_INDEX		0x28 /* Some commands need a scratch store */

Any specific reason for using an index divisible by 8? Afaik this is an
index, and the hw multiplies by 4 on it's own. So looks a bit puzzling
when reading (since iirc only 0x21 is used anywhere else, in some dri1
stuff).
-Daniel
>  
>  void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring);
>  
> -- 
> 1.7.9.5
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

  reply	other threads:[~2012-09-25  8:54 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2012-09-19 20:28 [PATCH 1/9] drm/i915: disable DOP clock gating on VLV and IVB Jesse Barnes
2012-09-19 20:28 ` [PATCH 2/9] drm/i915: implement WaForceL3Serialization " Jesse Barnes
2012-09-19 20:28 ` [PATCH 3/9] drm/i915: add a HSW scratch location for flush commands Jesse Barnes
2012-09-25  8:54   ` Daniel Vetter [this message]
2012-09-25 11:08     ` Jesse Barnes
2012-09-25 11:47       ` Daniel Vetter
2012-09-25 12:08         ` Jesse Barnes
2012-09-19 20:28 ` [PATCH 4/9] drm/i915: add post-flush store dw workaround Jesse Barnes
2012-09-25  8:49   ` Daniel Vetter
2012-09-25 11:07     ` Jesse Barnes
2012-09-19 20:28 ` [PATCH 5/9] drm/i915: implement WaDisableEarlyCull for VLV and IVB Jesse Barnes
2012-09-19 20:29 ` [PATCH 6/9] drm/i915: implement WaDisablePSDDualDispatchEnable on IVB and VLV Jesse Barnes
2012-09-25  8:51   ` Daniel Vetter
2012-10-01 16:52     ` Lespiau, Damien
2012-10-01 16:56       ` Jesse Barnes
2012-10-01 17:07         ` Lespiau, Damien
2012-10-01 16:57   ` Lespiau, Damien
2012-09-19 20:29 ` [PATCH 7/9] drm/i915: limit VLV IRQ enables to those we use Jesse Barnes
2012-09-26 14:16   ` Daniel Vetter
2012-09-19 20:29 ` [PATCH 8/9] drm/i915: TLB invalidation with MI_FLUSH_SW requires a post-sync op Jesse Barnes
2012-09-19 20:29 ` [PATCH 9/9] drm/i915: PIPE_CONTROL TLB invalidate requires CS stall Jesse Barnes
2012-09-19 21:41 ` [PATCH 1/9] drm/i915: disable DOP clock gating on VLV and IVB Ben Widawsky
2012-09-19 22:06   ` Jesse Barnes

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