From: Ben Widawsky <ben@bwidawsk.net>
To: Jesse Barnes <jbarnes@virtuousgeek.org>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 03/12] drm/i915: implement WaDisableDopClockGatingisable on VLV and IVB
Date: Tue, 2 Oct 2012 16:28:49 -0700 [thread overview]
Message-ID: <20121002162849.19de98d8@bwidawsk.net> (raw)
In-Reply-To: <1349217826-2538-4-git-send-email-jbarnes@virtuousgeek.org>
On Tue, 2 Oct 2012 17:43:37 -0500
Jesse Barnes <jbarnes@virtuousgeek.org> wrote:
> v2: use correct register
>
> References: https://bugs.freedesktop.org/show_bug.cgi?id=50233
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_pm.c | 8 +++++++-
> 2 files changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 58935a3..3b75052 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3446,6 +3446,7 @@
>
> #define GEN7_L3_CHICKEN_MODE_REGISTER 0xB030
> #define GEN7_WA_L3_CHICKEN_MODE 0x20000000
> +#define GEN7_WA_DOP_CLOCK_GATING_DISABLE 0x08000000
Looks like this doesn't belong in this patch.
>
> /* WaCatErrorRejectionIssue */
> #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG 0x9030
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index f7344c9..6be5910 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3545,7 +3545,9 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
> I915_WRITE(GEN7_L3CNTLREG1,
> GEN7_WA_FOR_GEN7_L3_CONTROL);
> I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
> - GEN7_WA_L3_CHICKEN_MODE);
> + GEN7_WA_L3_CHICKEN_MODE);
> + I915_WRITE(GEN7_ROW_CHICKEN2,
> + _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
>
> /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
> * gating disable must be set. Failure to set it results in
> @@ -3617,6 +3619,10 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
> I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS);
> I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
>
> + /* WaDisableDopClockGating */
> + I915_WRITE(GEN7_ROW_CHICKEN2,
> + _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
> +
> /* This is required by WaCatErrorRejectionIssue */
> I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
> I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
I think you're missing the GT2 disable.
--
Ben Widawsky, Intel Open Source Technology Center
next prev parent reply other threads:[~2012-10-02 23:29 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-10-02 22:43 Updated workaround & VLV fixes Jesse Barnes
2012-10-02 22:43 ` [PATCH 01/12] drm/i915: add more clock gating regs for gen7, make sure writes happen Jesse Barnes
2012-10-02 23:14 ` Ben Widawsky
2012-10-02 22:43 ` [PATCH 02/12] drm/i915: implement WaDisableL3CacheAging on VLV Jesse Barnes
2012-10-02 23:01 ` Daniel Vetter
2012-10-02 23:09 ` Ben Widawsky
2012-10-02 23:14 ` Ben Widawsky
2012-10-02 22:43 ` [PATCH 03/12] drm/i915: implement WaDisableDopClockGatingisable on VLV and IVB Jesse Barnes
2012-10-02 23:28 ` Ben Widawsky [this message]
2012-10-02 22:43 ` [PATCH 04/12] drm/i915: implement WaForceL3Serialization " Jesse Barnes
2012-10-02 23:32 ` Ben Widawsky
2012-10-03 7:24 ` Daniel Vetter
2012-10-02 22:43 ` [PATCH 05/12] drm/i915: implement WaGTEnableMiFlush on VLV Jesse Barnes
2012-10-02 23:35 ` Ben Widawsky
2012-10-02 22:43 ` [PATCH 06/12] drm/i915: implement WaDisableVLVClockGating_VBIIssue " Jesse Barnes
2012-10-02 23:38 ` Ben Widawsky
2012-10-02 22:43 ` [PATCH 07/12] drm/i915: implement WaDisableEarlyCull for VLV and IVB Jesse Barnes
2012-10-02 23:44 ` Ben Widawsky
2012-10-03 7:23 ` Daniel Vetter
2012-10-10 20:04 ` Paulo Zanoni
2012-10-10 21:13 ` Lespiau, Damien
2012-10-02 22:43 ` [PATCH 08/12] drm/i915: implement WaDisablePSDDualDispatchEnable on IVB Jesse Barnes
2012-10-02 23:51 ` Ben Widawsky
2012-10-02 23:58 ` Ben Widawsky
2012-10-02 22:43 ` [PATCH 09/12] drm/i915: limit VLV IRQ enables to those we use Jesse Barnes
2012-10-02 23:53 ` Ben Widawsky
2012-10-02 22:43 ` [PATCH 10/12] drm/i915: TLB invalidation with MI_FLUSH_SW requires a post-sync op Jesse Barnes
2012-10-03 0:14 ` Ben Widawsky
2012-10-03 7:20 ` Daniel Vetter
2012-10-04 8:32 ` Daniel Vetter
2012-10-04 14:39 ` Jesse Barnes
2012-10-04 14:49 ` Daniel Vetter
2012-10-04 14:54 ` Jesse Barnes
2012-10-02 22:43 ` [PATCH 11/12] drm/i915: PIPE_CONTROL TLB invalidate requires CS stall Jesse Barnes
2012-10-02 22:43 ` [PATCH 12/12] drm/i915: set swizzling to none on VLV Jesse Barnes
2012-10-03 7:15 ` Daniel Vetter
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