From: Ben Widawsky <ben@bwidawsk.net>
To: Jesse Barnes <jbarnes@virtuousgeek.org>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 04/12] drm/i915: implement WaForceL3Serialization on VLV and IVB
Date: Tue, 2 Oct 2012 16:32:44 -0700 [thread overview]
Message-ID: <20121002163244.7e89a20e@bwidawsk.net> (raw)
In-Reply-To: <1349217826-2538-5-git-send-email-jbarnes@virtuousgeek.org>
On Tue, 2 Oct 2012 17:43:38 -0500
Jesse Barnes <jbarnes@virtuousgeek.org> wrote:
> References: https://bugs.freedesktop.org/show_bug.cgi?id=50250
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 3 +++
> drivers/gpu/drm/i915/intel_pm.c | 8 ++++++++
> 2 files changed, 11 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 3b75052..c75539b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3448,6 +3448,9 @@
> #define GEN7_WA_L3_CHICKEN_MODE 0x20000000
> #define GEN7_WA_DOP_CLOCK_GATING_DISABLE 0x08000000
>
> +#define GEN7_L3SQCREG4 0xb034
> +#define L3SQ_URB_READ_CAM_MATCH_DISABLE (1<<27)
> +
> /* WaCatErrorRejectionIssue */
> #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG 0x9030
> #define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1<<11)
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 6be5910..0659317 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3549,6 +3549,10 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
> I915_WRITE(GEN7_ROW_CHICKEN2,
> _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
>
> + /* WaForceL3Serialization */
> + I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
> + ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
> +
> /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
> * gating disable must be set. Failure to set it results in
> * flickering pixels due to Z write ordering failures after
> @@ -3623,6 +3627,10 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
> I915_WRITE(GEN7_ROW_CHICKEN2,
> _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
>
> + /* WaForceL3Serialization */
> + I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
> + ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
> +
> /* This is required by WaCatErrorRejectionIssue */
> I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
> I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
--
Ben Widawsky, Intel Open Source Technology Center
next prev parent reply other threads:[~2012-10-02 23:32 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-10-02 22:43 Updated workaround & VLV fixes Jesse Barnes
2012-10-02 22:43 ` [PATCH 01/12] drm/i915: add more clock gating regs for gen7, make sure writes happen Jesse Barnes
2012-10-02 23:14 ` Ben Widawsky
2012-10-02 22:43 ` [PATCH 02/12] drm/i915: implement WaDisableL3CacheAging on VLV Jesse Barnes
2012-10-02 23:01 ` Daniel Vetter
2012-10-02 23:09 ` Ben Widawsky
2012-10-02 23:14 ` Ben Widawsky
2012-10-02 22:43 ` [PATCH 03/12] drm/i915: implement WaDisableDopClockGatingisable on VLV and IVB Jesse Barnes
2012-10-02 23:28 ` Ben Widawsky
2012-10-02 22:43 ` [PATCH 04/12] drm/i915: implement WaForceL3Serialization " Jesse Barnes
2012-10-02 23:32 ` Ben Widawsky [this message]
2012-10-03 7:24 ` Daniel Vetter
2012-10-02 22:43 ` [PATCH 05/12] drm/i915: implement WaGTEnableMiFlush on VLV Jesse Barnes
2012-10-02 23:35 ` Ben Widawsky
2012-10-02 22:43 ` [PATCH 06/12] drm/i915: implement WaDisableVLVClockGating_VBIIssue " Jesse Barnes
2012-10-02 23:38 ` Ben Widawsky
2012-10-02 22:43 ` [PATCH 07/12] drm/i915: implement WaDisableEarlyCull for VLV and IVB Jesse Barnes
2012-10-02 23:44 ` Ben Widawsky
2012-10-03 7:23 ` Daniel Vetter
2012-10-10 20:04 ` Paulo Zanoni
2012-10-10 21:13 ` Lespiau, Damien
2012-10-02 22:43 ` [PATCH 08/12] drm/i915: implement WaDisablePSDDualDispatchEnable on IVB Jesse Barnes
2012-10-02 23:51 ` Ben Widawsky
2012-10-02 23:58 ` Ben Widawsky
2012-10-02 22:43 ` [PATCH 09/12] drm/i915: limit VLV IRQ enables to those we use Jesse Barnes
2012-10-02 23:53 ` Ben Widawsky
2012-10-02 22:43 ` [PATCH 10/12] drm/i915: TLB invalidation with MI_FLUSH_SW requires a post-sync op Jesse Barnes
2012-10-03 0:14 ` Ben Widawsky
2012-10-03 7:20 ` Daniel Vetter
2012-10-04 8:32 ` Daniel Vetter
2012-10-04 14:39 ` Jesse Barnes
2012-10-04 14:49 ` Daniel Vetter
2012-10-04 14:54 ` Jesse Barnes
2012-10-02 22:43 ` [PATCH 11/12] drm/i915: PIPE_CONTROL TLB invalidate requires CS stall Jesse Barnes
2012-10-02 22:43 ` [PATCH 12/12] drm/i915: set swizzling to none on VLV Jesse Barnes
2012-10-03 7:15 ` Daniel Vetter
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