From: Joerg Roedel <joro-zLv9SwRftAIdnm+yROfE0A@public.gmane.org>
To: suravee.suthikulpanit-5C7GfCeVMHo@public.gmane.org
Cc: iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Subject: Re: [PATCH 3/3] iommu/amd: Re-enable IOMMU event log interrupt after handling.
Date: Tue, 2 Apr 2013 16:50:42 +0200 [thread overview]
Message-ID: <20130402145041.GD15687@8bytes.org> (raw)
In-Reply-To: <1364428312-2611-1-git-send-email-suravee.suthikulpanit-5C7GfCeVMHo@public.gmane.org>
On Wed, Mar 27, 2013 at 06:51:52PM -0500, suravee.suthikulpanit-5C7GfCeVMHo@public.gmane.org wrote:
> From: Suravee Suthikulpanit <suravee.suthikulpanit-5C7GfCeVMHo@public.gmane.org>
>
> Current driver does not clear the IOMMU event log interrupt bit
> in the IOMMU status register after processing an interrupt.
> This causes the IOMMU hardware to generate event log interrupt only once.
> This has been observed in both IOMMU v1 and V2 hardware.
> This patch clears the bit by writing 1 to bit 1 of the IOMMU
> status register (MMIO Offset 2020h)
>
> Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit-5C7GfCeVMHo@public.gmane.org>
Applied to x86/amd, thanks.
WARNING: multiple messages have this Message-ID (diff)
From: Joerg Roedel <joro@8bytes.org>
To: suravee.suthikulpanit@amd.com
Cc: iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 3/3] iommu/amd: Re-enable IOMMU event log interrupt after handling.
Date: Tue, 2 Apr 2013 16:50:42 +0200 [thread overview]
Message-ID: <20130402145041.GD15687@8bytes.org> (raw)
In-Reply-To: <1364428312-2611-1-git-send-email-suravee.suthikulpanit@amd.com>
On Wed, Mar 27, 2013 at 06:51:52PM -0500, suravee.suthikulpanit@amd.com wrote:
> From: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
>
> Current driver does not clear the IOMMU event log interrupt bit
> in the IOMMU status register after processing an interrupt.
> This causes the IOMMU hardware to generate event log interrupt only once.
> This has been observed in both IOMMU v1 and V2 hardware.
> This patch clears the bit by writing 1 to bit 1 of the IOMMU
> status register (MMIO Offset 2020h)
>
> Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Applied to x86/amd, thanks.
next prev parent reply other threads:[~2013-04-02 14:50 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-03-27 23:51 [PATCH 3/3] iommu/amd: Re-enable IOMMU event log interrupt after handling suravee.suthikulpanit
2013-03-27 23:51 ` suravee.suthikulpanit
[not found] ` <1364428312-2611-1-git-send-email-suravee.suthikulpanit-5C7GfCeVMHo@public.gmane.org>
2013-04-02 14:50 ` Joerg Roedel [this message]
2013-04-02 14:50 ` Joerg Roedel
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