* [PATCH 3/3] iommu/amd: Re-enable IOMMU event log interrupt after handling.
@ 2013-03-27 23:51 ` suravee.suthikulpanit
0 siblings, 0 replies; 4+ messages in thread
From: suravee.suthikulpanit @ 2013-03-27 23:51 UTC (permalink / raw)
To: iommu, joro; +Cc: linux-kernel, Suravee Suthikulpanit
From: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Current driver does not clear the IOMMU event log interrupt bit
in the IOMMU status register after processing an interrupt.
This causes the IOMMU hardware to generate event log interrupt only once.
This has been observed in both IOMMU v1 and V2 hardware.
This patch clears the bit by writing 1 to bit 1 of the IOMMU
status register (MMIO Offset 2020h)
Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
---
drivers/iommu/amd_iommu.c | 3 +++
drivers/iommu/amd_iommu_types.h | 1 +
2 files changed, 4 insertions(+)
diff --git a/drivers/iommu/amd_iommu.c b/drivers/iommu/amd_iommu.c
index 30ac0cb..13a4f63 100644
--- a/drivers/iommu/amd_iommu.c
+++ b/drivers/iommu/amd_iommu.c
@@ -809,6 +809,9 @@ static void iommu_poll_events(struct amd_iommu *iommu)
u32 head, tail;
unsigned long flags;
+ /* enable event interrupts again */
+ writel(MMIO_STATUS_EVT_INT_MASK, iommu->mmio_base + MMIO_STATUS_OFFSET);
+
spin_lock_irqsave(&iommu->lock, flags);
head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
diff --git a/drivers/iommu/amd_iommu_types.h b/drivers/iommu/amd_iommu_types.h
index e38ab43..083f98c 100644
--- a/drivers/iommu/amd_iommu_types.h
+++ b/drivers/iommu/amd_iommu_types.h
@@ -99,6 +99,7 @@
#define PASID_MASK 0x000fffff
/* MMIO status bits */
+#define MMIO_STATUS_EVT_INT_MASK (1 << 1)
#define MMIO_STATUS_COM_WAIT_INT_MASK (1 << 2)
#define MMIO_STATUS_PPR_INT_MASK (1 << 6)
--
1.7.10.4
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH 3/3] iommu/amd: Re-enable IOMMU event log interrupt after handling.
@ 2013-03-27 23:51 ` suravee.suthikulpanit
0 siblings, 0 replies; 4+ messages in thread
From: suravee.suthikulpanit @ 2013-03-27 23:51 UTC (permalink / raw)
To: iommu, joro; +Cc: linux-kernel, Suravee Suthikulpanit
From: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Current driver does not clear the IOMMU event log interrupt bit
in the IOMMU status register after processing an interrupt.
This causes the IOMMU hardware to generate event log interrupt only once.
This has been observed in both IOMMU v1 and V2 hardware.
This patch clears the bit by writing 1 to bit 1 of the IOMMU
status register (MMIO Offset 2020h)
Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
---
drivers/iommu/amd_iommu.c | 3 +++
drivers/iommu/amd_iommu_types.h | 1 +
2 files changed, 4 insertions(+)
diff --git a/drivers/iommu/amd_iommu.c b/drivers/iommu/amd_iommu.c
index 30ac0cb..13a4f63 100644
--- a/drivers/iommu/amd_iommu.c
+++ b/drivers/iommu/amd_iommu.c
@@ -809,6 +809,9 @@ static void iommu_poll_events(struct amd_iommu *iommu)
u32 head, tail;
unsigned long flags;
+ /* enable event interrupts again */
+ writel(MMIO_STATUS_EVT_INT_MASK, iommu->mmio_base + MMIO_STATUS_OFFSET);
+
spin_lock_irqsave(&iommu->lock, flags);
head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
diff --git a/drivers/iommu/amd_iommu_types.h b/drivers/iommu/amd_iommu_types.h
index e38ab43..083f98c 100644
--- a/drivers/iommu/amd_iommu_types.h
+++ b/drivers/iommu/amd_iommu_types.h
@@ -99,6 +99,7 @@
#define PASID_MASK 0x000fffff
/* MMIO status bits */
+#define MMIO_STATUS_EVT_INT_MASK (1 << 1)
#define MMIO_STATUS_COM_WAIT_INT_MASK (1 << 2)
#define MMIO_STATUS_PPR_INT_MASK (1 << 6)
--
1.7.10.4
^ permalink raw reply related [flat|nested] 4+ messages in thread
[parent not found: <1364428312-2611-1-git-send-email-suravee.suthikulpanit-5C7GfCeVMHo@public.gmane.org>]
* Re: [PATCH 3/3] iommu/amd: Re-enable IOMMU event log interrupt after handling.
2013-03-27 23:51 ` suravee.suthikulpanit
@ 2013-04-02 14:50 ` Joerg Roedel
-1 siblings, 0 replies; 4+ messages in thread
From: Joerg Roedel @ 2013-04-02 14:50 UTC (permalink / raw)
To: suravee.suthikulpanit-5C7GfCeVMHo
Cc: iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
On Wed, Mar 27, 2013 at 06:51:52PM -0500, suravee.suthikulpanit-5C7GfCeVMHo@public.gmane.org wrote:
> From: Suravee Suthikulpanit <suravee.suthikulpanit-5C7GfCeVMHo@public.gmane.org>
>
> Current driver does not clear the IOMMU event log interrupt bit
> in the IOMMU status register after processing an interrupt.
> This causes the IOMMU hardware to generate event log interrupt only once.
> This has been observed in both IOMMU v1 and V2 hardware.
> This patch clears the bit by writing 1 to bit 1 of the IOMMU
> status register (MMIO Offset 2020h)
>
> Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit-5C7GfCeVMHo@public.gmane.org>
Applied to x86/amd, thanks.
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH 3/3] iommu/amd: Re-enable IOMMU event log interrupt after handling.
@ 2013-04-02 14:50 ` Joerg Roedel
0 siblings, 0 replies; 4+ messages in thread
From: Joerg Roedel @ 2013-04-02 14:50 UTC (permalink / raw)
To: suravee.suthikulpanit; +Cc: iommu, linux-kernel
On Wed, Mar 27, 2013 at 06:51:52PM -0500, suravee.suthikulpanit@amd.com wrote:
> From: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
>
> Current driver does not clear the IOMMU event log interrupt bit
> in the IOMMU status register after processing an interrupt.
> This causes the IOMMU hardware to generate event log interrupt only once.
> This has been observed in both IOMMU v1 and V2 hardware.
> This patch clears the bit by writing 1 to bit 1 of the IOMMU
> status register (MMIO Offset 2020h)
>
> Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Applied to x86/amd, thanks.
^ permalink raw reply [flat|nested] 4+ messages in thread
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2013-03-27 23:51 [PATCH 3/3] iommu/amd: Re-enable IOMMU event log interrupt after handling suravee.suthikulpanit
2013-03-27 23:51 ` suravee.suthikulpanit
[not found] ` <1364428312-2611-1-git-send-email-suravee.suthikulpanit-5C7GfCeVMHo@public.gmane.org>
2013-04-02 14:50 ` Joerg Roedel
2013-04-02 14:50 ` Joerg Roedel
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