[PATCH 1/7] drm/i915: Support PCH no display

[PATCH 1/7] drm/i915: Support PCH no display

[Ben Widawsky]

GEN supports a fusing option which subtracts the PCH display (making the
CPU display also useless). In this configuration MMIO which gets decoded
to a certain range will hang the CPU.

For us, this is sort of the equivalent of having no pipes, and we can
easily modify some code to not do certain things with no pipes.

v2: Moved the num pipes check up in the call chain, and removed extra
checks noted by Daniel. For more details, see:
http://lists.freedesktop.org/archives/intel-gfx/2013-March/025746.html

v3: Drop the intel_setup_overlay check (Daniel)

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
 drivers/gpu/drm/i915/i915_dma.c      | 20 ++++++++++++++------
 drivers/gpu/drm/i915/intel_display.c |  3 +++
 drivers/gpu/drm/i915/intel_fb.c      |  3 +++
 3 files changed, 20 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index ebcfe2e..d925504 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1322,6 +1322,10 @@ static int i915_load_modeset_init(struct drm_device *dev)
 	/* Always safe in the mode setting case. */
 	/* FIXME: do pre/post-mode set stuff in core KMS code */
 	dev->vblank_disable_allowed = 1;
+	if (INTEL_INFO(dev)->num_pipes == 0) {
+		dev_priv->mm.suspended = 0;
+		return 0;
+	}
 
 	ret = intel_fbdev_init(dev);
 	if (ret)
@@ -1630,9 +1634,11 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
 	mutex_init(&dev_priv->rps.hw_lock);
 	mutex_init(&dev_priv->modeset_restore_lock);
 
-	ret = drm_vblank_init(dev, INTEL_INFO(dev)->num_pipes);
-	if (ret)
-		goto out_gem_unload;
+	if (INTEL_INFO(dev)->num_pipes) {
+		ret = drm_vblank_init(dev, INTEL_INFO(dev)->num_pipes);
+		if (ret)
+			goto out_gem_unload;
+	}
 
 	/* Start out suspended */
 	dev_priv->mm.suspended = 1;
@@ -1647,9 +1653,11 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
 
 	i915_setup_sysfs(dev);
 
-	/* Must be done after probing outputs */
-	intel_opregion_init(dev);
-	acpi_video_register();
+	if (INTEL_INFO(dev)->num_pipes) {
+		/* Must be done after probing outputs */
+		intel_opregion_init(dev);
+		acpi_video_register();
+	}
 
 	if (IS_GEN5(dev))
 		intel_gpu_ips_init(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index b3b22d7..f2a1cce 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8872,6 +8872,9 @@ void intel_modeset_init(struct drm_device *dev)
 
 	intel_init_pm(dev);
 
+	if (INTEL_INFO(dev)->num_pipes == 0)
+		return;
+
 	intel_init_display(dev);
 
 	if (IS_GEN2(dev)) {
diff --git a/drivers/gpu/drm/i915/intel_fb.c b/drivers/gpu/drm/i915/intel_fb.c
index f203418..5f9836b 100644
--- a/drivers/gpu/drm/i915/intel_fb.c
+++ b/drivers/gpu/drm/i915/intel_fb.c
@@ -280,6 +280,9 @@ void intel_fb_restore_mode(struct drm_device *dev)
 	struct drm_mode_config *config = &dev->mode_config;
 	struct drm_plane *plane;
 
+	if (INTEL_INFO(dev)->num_pipes == 0)
+		return;
+
 	drm_modeset_lock_all(dev);
 
 	ret = drm_fb_helper_restore_fbdev_mode(&dev_priv->fbdev->helper);
-- 
1.8.2

[PATCH 2/7] drm/i915: PCH_NOP

[Ben Widawsky]

Given certain fusing options discussed in the previous patch, it's
possible to end up with platforms that normally have PCH but that PCH
doesn't actually exist. In many cases, this is easily remedied with
setting 0 pipes. This covers the other corners.

Requiring this is a symptom of improper code splitting (using
HAS_PCH_SPLIT instead of proper GEN checking, basically). I do not want
to fix this.

v2: Remove PCH reflck after change in previous patch (Daniel)

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
 drivers/gpu/drm/i915/i915_drv.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1657d873..a6123a0 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -461,6 +461,7 @@ enum intel_pch {
 	PCH_IBX,	/* Ibexpeak PCH */
 	PCH_CPT,	/* Cougarpoint PCH */
 	PCH_LPT,	/* Lynxpoint PCH */
+	PCH_NOP,
 };
 
 enum intel_sbi_destination {
@@ -1352,6 +1353,7 @@ struct drm_i915_file_private {
 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
+#define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
 
 #define HAS_FORCE_WAKE(dev) (INTEL_INFO(dev)->has_force_wake)
-- 
1.8.2

[PATCH 3/7] drm/i915: Don't touch South Display when PCH_NOP

[Ben Widawsky]

Interrupts, clock gating, LVDS, and GMBUS are all within the, "this will
be bad for CPU" range when we have PCH_NOP.

There is a bit of a hack in init clock gating. We want to do most of the
clock gating, but the part we skip will hang the system. It could
probably be abstracted a bit better, but I don't feel it's too
unsightly.

v2: Use inverse HAS_PCH_NOP check (Jani)

v3: Actually do what I claimed in v2 (spotted by Daniel)
Merge Ivybridge IRQ handler PCH check to decrease whitespace (Daniel)
Move LVDS bail into this patch (Ben)

v4: logical rebase conflict resolution with SDEIIR (Ben)

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
 drivers/gpu/drm/i915/i915_irq.c   | 24 +++++++++++++++++-------
 drivers/gpu/drm/i915/intel_bios.c |  3 +++
 drivers/gpu/drm/i915/intel_i2c.c  |  4 +++-
 drivers/gpu/drm/i915/intel_pm.c   |  3 ++-
 4 files changed, 25 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 5fc178e..324c727 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -704,7 +704,7 @@ static irqreturn_t ivybridge_irq_handler(int irq, void *arg)
 {
 	struct drm_device *dev = (struct drm_device *) arg;
 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
-	u32 de_iir, gt_iir, de_ier, pm_iir, sde_ier;
+	u32 de_iir, gt_iir, de_ier, pm_iir, sde_ier = 0;
 	irqreturn_t ret = IRQ_NONE;
 	int i;
 
@@ -719,9 +719,11 @@ static irqreturn_t ivybridge_irq_handler(int irq, void *arg)
 	 * able to process them after we restore SDEIER (as soon as we restore
 	 * it, we'll get an interrupt if SDEIIR still has something to process
 	 * due to its back queue). */
-	sde_ier = I915_READ(SDEIER);
-	I915_WRITE(SDEIER, 0);
-	POSTING_READ(SDEIER);
+	if (!HAS_PCH_NOP(dev)) {
+		sde_ier = I915_READ(SDEIER);
+		I915_WRITE(SDEIER, 0);
+		POSTING_READ(SDEIER);
+	}
 
 	gt_iir = I915_READ(GTIIR);
 	if (gt_iir) {
@@ -748,7 +750,7 @@ static irqreturn_t ivybridge_irq_handler(int irq, void *arg)
 		}
 
 		/* check event from PCH */
-		if (de_iir & DE_PCH_EVENT_IVB) {
+		if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
 			u32 pch_iir = I915_READ(SDEIIR);
 
 			cpt_irq_handler(dev, pch_iir);
@@ -771,8 +773,10 @@ static irqreturn_t ivybridge_irq_handler(int irq, void *arg)
 
 	I915_WRITE(DEIER, de_ier);
 	POSTING_READ(DEIER);
-	I915_WRITE(SDEIER, sde_ier);
-	POSTING_READ(SDEIER);
+	if (!HAS_PCH_NOP(dev)) {
+		I915_WRITE(SDEIER, sde_ier);
+		POSTING_READ(SDEIER);
+	}
 
 	return ret;
 }
@@ -1972,6 +1976,9 @@ static void ironlake_irq_preinstall(struct drm_device *dev)
 	I915_WRITE(GTIER, 0x0);
 	POSTING_READ(GTIER);
 
+	if (HAS_PCH_NOP(dev))
+		return;
+
 	/* south display irq */
 	I915_WRITE(SDEIMR, 0xffffffff);
 	I915_WRITE(SDEIER, 0x0);
@@ -2044,6 +2051,9 @@ static void ibx_irq_postinstall(struct drm_device *dev)
 		       SDE_GMBUS_CPT |
 		       SDE_AUX_MASK_CPT;
 
+	if (HAS_PCH_NOP(dev))
+		return;
+
 	I915_WRITE(SDEIIR, I915_READ(SDEIIR));
 	I915_WRITE(SDEIMR, ~mask);
 	I915_WRITE(SDEIER, mask);
diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index 55ffba1..194df27 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -692,6 +692,9 @@ intel_parse_bios(struct drm_device *dev)
 	struct bdb_header *bdb = NULL;
 	u8 __iomem *bios = NULL;
 
+	if (HAS_PCH_NOP(dev))
+		return -ENODEV;
+
 	init_vbt_defaults(dev_priv);
 
 	/* XXX Should this validation be moved to intel_opregion.c? */
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index ef4744e..5d24503 100644
--- a/drivers/gpu/drm/i915/intel_i2c.c
+++ b/drivers/gpu/drm/i915/intel_i2c.c
@@ -522,7 +522,9 @@ int intel_setup_gmbus(struct drm_device *dev)
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	int ret, i;
 
-	if (HAS_PCH_SPLIT(dev))
+	if (HAS_PCH_NOP(dev))
+		return 0;
+	else if (HAS_PCH_SPLIT(dev))
 		dev_priv->gpio_mmio_base = PCH_GPIOA - GPIOA;
 	else if (IS_VALLEYVIEW(dev))
 		dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 8a3d89e..eda2fb0 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3874,7 +3874,8 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
 	snpcr |= GEN6_MBC_SNPCR_MED;
 	I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
 
-	cpt_init_clock_gating(dev);
+	if (!HAS_PCH_NOP(dev))
+		cpt_init_clock_gating(dev);
 
 	gen6_check_mch_setup(dev);
 }
-- 
1.8.2

[PATCH 4/7] drm/i915: PCH_NOP suspend/resume

[Ben Widawsky]

More registers we can't write.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
 drivers/gpu/drm/i915/i915_suspend.c | 58 +++++++++++++++++++++++++++----------
 1 file changed, 42 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index 41f0fde..7f58c82 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -334,11 +334,19 @@ int i915_save_state(struct drm_device *dev)
 
 	mutex_lock(&dev->struct_mutex);
 
-	i915_save_display(dev);
+	if (!HAS_PCH_NOP(dev))
+		i915_save_display(dev);
 
 	if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
 		/* Interrupt state */
-		if (HAS_PCH_SPLIT(dev)) {
+		if (HAS_PCH_NOP(dev)) {
+			dev_priv->regfile.saveDEIER = I915_READ(DEIER);
+			dev_priv->regfile.saveDEIMR = I915_READ(DEIMR);
+			dev_priv->regfile.saveGTIER = I915_READ(GTIER);
+			dev_priv->regfile.saveGTIMR = I915_READ(GTIMR);
+			dev_priv->regfile.saveMCHBAR_RENDER_STANDBY =
+				I915_READ(RSTDBYCTL);
+		} else if (HAS_PCH_SPLIT(dev)) {
 			dev_priv->regfile.saveDEIER = I915_READ(DEIER);
 			dev_priv->regfile.saveDEIMR = I915_READ(DEIMR);
 			dev_priv->regfile.saveGTIER = I915_READ(GTIER);
@@ -362,13 +370,19 @@ int i915_save_state(struct drm_device *dev)
 	/* Memory Arbitration state */
 	dev_priv->regfile.saveMI_ARB_STATE = I915_READ(MI_ARB_STATE);
 
-	/* Scratch space */
-	for (i = 0; i < 16; i++) {
-		dev_priv->regfile.saveSWF0[i] = I915_READ(SWF00 + (i << 2));
-		dev_priv->regfile.saveSWF1[i] = I915_READ(SWF10 + (i << 2));
+	if (!HAS_PCH_NOP(dev)) {
+		/* Scratch space
+		 * XXX: Do we really need this for kms? */
+		for (i = 0; i < 16; i++) {
+			dev_priv->regfile.saveSWF0[i] =
+				I915_READ(SWF00 + (i << 2));
+			dev_priv->regfile.saveSWF1[i] =
+				I915_READ(SWF10 + (i << 2));
+		}
+		for (i = 0; i < 3; i++)
+			dev_priv->regfile.saveSWF2[i] =
+				I915_READ(SWF30 + (i << 2));
 	}
-	for (i = 0; i < 3; i++)
-		dev_priv->regfile.saveSWF2[i] = I915_READ(SWF30 + (i << 2));
 
 	mutex_unlock(&dev->struct_mutex);
 
@@ -384,11 +398,17 @@ int i915_restore_state(struct drm_device *dev)
 
 	mutex_lock(&dev->struct_mutex);
 
-	i915_restore_display(dev);
+	if (!HAS_PCH_NOP(dev))
+		i915_restore_display(dev);
 
 	if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
 		/* Interrupt state */
-		if (HAS_PCH_SPLIT(dev)) {
+		if (HAS_PCH_NOP(dev)) {
+			I915_WRITE(DEIER, dev_priv->regfile.saveDEIER);
+			I915_WRITE(DEIMR, dev_priv->regfile.saveDEIMR);
+			I915_WRITE(GTIER, dev_priv->regfile.saveGTIER);
+			I915_WRITE(GTIMR, dev_priv->regfile.saveGTIMR);
+		} else if (HAS_PCH_SPLIT(dev)) {
 			I915_WRITE(DEIER, dev_priv->regfile.saveDEIER);
 			I915_WRITE(DEIMR, dev_priv->regfile.saveDEIMR);
 			I915_WRITE(GTIER, dev_priv->regfile.saveGTIER);
@@ -408,16 +428,22 @@ int i915_restore_state(struct drm_device *dev)
 	/* Memory arbitration state */
 	I915_WRITE(MI_ARB_STATE, dev_priv->regfile.saveMI_ARB_STATE | 0xffff0000);
 
-	for (i = 0; i < 16; i++) {
-		I915_WRITE(SWF00 + (i << 2), dev_priv->regfile.saveSWF0[i]);
-		I915_WRITE(SWF10 + (i << 2), dev_priv->regfile.saveSWF1[i]);
+	if (!HAS_PCH_NOP(dev)) {
+		for (i = 0; i < 16; i++) {
+			I915_WRITE(SWF00 + (i << 2),
+				   dev_priv->regfile.saveSWF0[i]);
+			I915_WRITE(SWF10 + (i << 2),
+				   dev_priv->regfile.saveSWF1[i]);
+		}
+		for (i = 0; i < 3; i++)
+			I915_WRITE(SWF30 + (i << 2),
+				   dev_priv->regfile.saveSWF2[i]);
 	}
-	for (i = 0; i < 3; i++)
-		I915_WRITE(SWF30 + (i << 2), dev_priv->regfile.saveSWF2[i]);
 
 	mutex_unlock(&dev->struct_mutex);
 
-	intel_i2c_reset(dev);
+	if (!HAS_PCH_NOP(dev))
+		intel_i2c_reset(dev);
 
 	return 0;
 }
-- 
1.8.2

Re: [PATCH 4/7] drm/i915: PCH_NOP suspend/resume

[Daniel Vetter]

On Fri, Apr 05, 2013 at 01:12:42PM -0700, Ben Widawsky wrote:
> More registers we can't write.
> 
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>

Fixed up a minor bug (at least I think it's one) in the irq uninstall
code. Note that this is also run on gpu hangs and resume, so relevant.

Also there's been a little conflict with Paulo's SDE irq handling fix in
-fixes. I recommend to base all feature work on top of -nightly to avoid
such issues. If there'll be a conflict when the patch applies only to
-nightly, but not dinq, I can fix this up when applying.

Can you please check whether I didn't break the PCH_NOP support?

Thanks, Daniel
> ---
>  drivers/gpu/drm/i915/i915_suspend.c | 58 +++++++++++++++++++++++++++----------
>  1 file changed, 42 insertions(+), 16 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
> index 41f0fde..7f58c82 100644
> --- a/drivers/gpu/drm/i915/i915_suspend.c
> +++ b/drivers/gpu/drm/i915/i915_suspend.c
> @@ -334,11 +334,19 @@ int i915_save_state(struct drm_device *dev)
>  
>  	mutex_lock(&dev->struct_mutex);
>  
> -	i915_save_display(dev);
> +	if (!HAS_PCH_NOP(dev))
> +		i915_save_display(dev);
>  
>  	if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
>  		/* Interrupt state */
> -		if (HAS_PCH_SPLIT(dev)) {
> +		if (HAS_PCH_NOP(dev)) {
> +			dev_priv->regfile.saveDEIER = I915_READ(DEIER);
> +			dev_priv->regfile.saveDEIMR = I915_READ(DEIMR);
> +			dev_priv->regfile.saveGTIER = I915_READ(GTIER);
> +			dev_priv->regfile.saveGTIMR = I915_READ(GTIMR);
> +			dev_priv->regfile.saveMCHBAR_RENDER_STANDBY =
> +				I915_READ(RSTDBYCTL);
> +		} else if (HAS_PCH_SPLIT(dev)) {
>  			dev_priv->regfile.saveDEIER = I915_READ(DEIER);
>  			dev_priv->regfile.saveDEIMR = I915_READ(DEIMR);
>  			dev_priv->regfile.saveGTIER = I915_READ(GTIER);
> @@ -362,13 +370,19 @@ int i915_save_state(struct drm_device *dev)
>  	/* Memory Arbitration state */
>  	dev_priv->regfile.saveMI_ARB_STATE = I915_READ(MI_ARB_STATE);
>  
> -	/* Scratch space */
> -	for (i = 0; i < 16; i++) {
> -		dev_priv->regfile.saveSWF0[i] = I915_READ(SWF00 + (i << 2));
> -		dev_priv->regfile.saveSWF1[i] = I915_READ(SWF10 + (i << 2));
> +	if (!HAS_PCH_NOP(dev)) {
> +		/* Scratch space
> +		 * XXX: Do we really need this for kms? */
> +		for (i = 0; i < 16; i++) {
> +			dev_priv->regfile.saveSWF0[i] =
> +				I915_READ(SWF00 + (i << 2));
> +			dev_priv->regfile.saveSWF1[i] =
> +				I915_READ(SWF10 + (i << 2));
> +		}
> +		for (i = 0; i < 3; i++)
> +			dev_priv->regfile.saveSWF2[i] =
> +				I915_READ(SWF30 + (i << 2));
>  	}
> -	for (i = 0; i < 3; i++)
> -		dev_priv->regfile.saveSWF2[i] = I915_READ(SWF30 + (i << 2));
>  
>  	mutex_unlock(&dev->struct_mutex);
>  
> @@ -384,11 +398,17 @@ int i915_restore_state(struct drm_device *dev)
>  
>  	mutex_lock(&dev->struct_mutex);
>  
> -	i915_restore_display(dev);
> +	if (!HAS_PCH_NOP(dev))
> +		i915_restore_display(dev);
>  
>  	if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
>  		/* Interrupt state */
> -		if (HAS_PCH_SPLIT(dev)) {
> +		if (HAS_PCH_NOP(dev)) {
> +			I915_WRITE(DEIER, dev_priv->regfile.saveDEIER);
> +			I915_WRITE(DEIMR, dev_priv->regfile.saveDEIMR);
> +			I915_WRITE(GTIER, dev_priv->regfile.saveGTIER);
> +			I915_WRITE(GTIMR, dev_priv->regfile.saveGTIMR);
> +		} else if (HAS_PCH_SPLIT(dev)) {
>  			I915_WRITE(DEIER, dev_priv->regfile.saveDEIER);
>  			I915_WRITE(DEIMR, dev_priv->regfile.saveDEIMR);
>  			I915_WRITE(GTIER, dev_priv->regfile.saveGTIER);
> @@ -408,16 +428,22 @@ int i915_restore_state(struct drm_device *dev)
>  	/* Memory arbitration state */
>  	I915_WRITE(MI_ARB_STATE, dev_priv->regfile.saveMI_ARB_STATE | 0xffff0000);
>  
> -	for (i = 0; i < 16; i++) {
> -		I915_WRITE(SWF00 + (i << 2), dev_priv->regfile.saveSWF0[i]);
> -		I915_WRITE(SWF10 + (i << 2), dev_priv->regfile.saveSWF1[i]);
> +	if (!HAS_PCH_NOP(dev)) {
> +		for (i = 0; i < 16; i++) {
> +			I915_WRITE(SWF00 + (i << 2),
> +				   dev_priv->regfile.saveSWF0[i]);
> +			I915_WRITE(SWF10 + (i << 2),
> +				   dev_priv->regfile.saveSWF1[i]);
> +		}
> +		for (i = 0; i < 3; i++)
> +			I915_WRITE(SWF30 + (i << 2),
> +				   dev_priv->regfile.saveSWF2[i]);
>  	}
> -	for (i = 0; i < 3; i++)
> -		I915_WRITE(SWF30 + (i << 2), dev_priv->regfile.saveSWF2[i]);
>  
>  	mutex_unlock(&dev->struct_mutex);
>  
> -	intel_i2c_reset(dev);
> +	if (!HAS_PCH_NOP(dev))
> +		intel_i2c_reset(dev);
>  
>  	return 0;
>  }
> -- 
> 1.8.2
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 4/7] drm/i915: PCH_NOP suspend/resume

[Daniel Vetter]

On Sat, Apr 06, 2013 at 07:41:44PM +0200, Daniel Vetter wrote:
> On Fri, Apr 05, 2013 at 01:12:42PM -0700, Ben Widawsky wrote:
> > More registers we can't write.
> > 
> > Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
> 
> Fixed up a minor bug (at least I think it's one) in the irq uninstall
> code. Note that this is also run on gpu hangs and resume, so relevant.
> 
> Also there's been a little conflict with Paulo's SDE irq handling fix in
> -fixes. I recommend to base all feature work on top of -nightly to avoid
> such issues. If there'll be a conflict when the patch applies only to
> -nightly, but not dinq, I can fix this up when applying.

Ok, I've embarassed myself here a bit and fixed up the ilk irq handler,
which isn't run at all on ivb. I've rectified that again.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

[PATCH 5/7] drm/i915: Don't wait for PCH on reset

[Ben Widawsky]

BIOS should be setting this, but in case it doesn't...

v2: Define the bits we actually want to clear (Jesse)
Make it an RMW op (Jesse)

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_gem.c | 6 ++++++
 drivers/gpu/drm/i915/i915_reg.h | 3 +++
 2 files changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 8a2cbee..f2d4970 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3991,6 +3991,12 @@ i915_gem_init_hw(struct drm_device *dev)
 	if (IS_HASWELL(dev) && (I915_READ(0x120010) == 1))
 		I915_WRITE(0x9008, I915_READ(0x9008) | 0xf0000);
 
+	if (HAS_PCH_NOP(dev)) {
+		u32 temp = I915_READ(GEN7_MSG_CTL);
+		temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
+		I915_WRITE(GEN7_MSG_CTL, temp);
+	}
+
 	i915_gem_l3_remap(dev);
 
 	i915_gem_init_swizzling(dev);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 50dba38..61b5b4f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3483,6 +3483,9 @@
 #define DISP_ARB_CTL	0x45000
 #define  DISP_TILE_SURFACE_SWIZZLING	(1<<13)
 #define  DISP_FBC_WM_DIS		(1<<15)
+#define GEN7_MSG_CTL	0x45010
+#define  WAIT_FOR_PCH_RESET_ACK		(1<<1)
+#define  WAIT_FOR_PCH_FLR_ACK		(1<<0)
 
 /* GEN7 chicken */
 #define GEN7_COMMON_SLICE_CHICKEN1		0x7010
-- 
1.8.2

[PATCH 6/7] drm/i915: Set PCH_NOP

[Ben Widawsky]

Set up PCH_NOP when we match a certain platform.

v2: Just do a num_pipes check + comment instead of trying to check the
platform (Daniel)

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
 drivers/gpu/drm/i915/i915_drv.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 6c4b13c..55211d7 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -392,6 +392,15 @@ void intel_detect_pch(struct drm_device *dev)
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct pci_dev *pch;
 
+	/* In all current cases, num_pipes is equivalent to the PCH_NOP setting
+	 * (which really amounts to a PCH but no South Display).
+	 */
+	if (INTEL_INFO(dev)->num_pipes == 0) {
+		dev_priv->pch_type = PCH_NOP;
+		dev_priv->num_pch_pll = 0;
+		return;
+	}
+
 	/*
 	 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 	 * make graphics device passthrough work easy for VMM, that only
-- 
1.8.2

[PATCH 7/7] drm/i915: Add a pipeless ivybridge configuration

[Ben Widawsky]

FIXME: This is based on some HW being used for a demo. We should
probably wait until we have confirmation on the IDs before upstreaming
this patch.

v2: Use GEN7_FEATURES (Chris)

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
 drivers/gpu/drm/i915/i915_drv.c | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 55211d7..8753f81 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -135,6 +135,16 @@ extern int intel_agp_enabled;
 	.subdevice = PCI_ANY_ID,		\
 	.driver_data = (unsigned long) info }
 
+#define INTEL_QUANTA_VGA_DEVICE(info) {		\
+	.class = PCI_BASE_CLASS_DISPLAY << 16,	\
+	.class_mask = 0xff0000,			\
+	.vendor = 0x8086,			\
+	.device = 0x16a,			\
+	.subvendor = 0x152d,			\
+	.subdevice = 0x8990,			\
+	.driver_data = (unsigned long) info }
+
+
 static const struct intel_device_info intel_i830_info = {
 	.gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
 	.has_overlay = 1, .overlay_needs_physical = 1,
@@ -267,6 +277,12 @@ static const struct intel_device_info intel_ivybridge_m_info = {
 	.is_mobile = 1,
 };
 
+static const struct intel_device_info intel_ivybridge_q_info = {
+	GEN7_FEATURES,
+	.is_ivybridge = 1,
+	.num_pipes = 0, /* legal, last one wins */
+};
+
 static const struct intel_device_info intel_valleyview_m_info = {
 	GEN7_FEATURES,
 	.is_mobile = 1,
@@ -337,6 +353,7 @@ static const struct pci_device_id pciidlist[] = {		/* aka */
 	INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
 	INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
 	INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
+	INTEL_QUANTA_VGA_DEVICE(&intel_ivybridge_q_info), /* Quanta transcode */
 	INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */
 	INTEL_VGA_DEVICE(0x0402, &intel_haswell_d_info), /* GT1 desktop */
 	INTEL_VGA_DEVICE(0x0412, &intel_haswell_d_info), /* GT2 desktop */
-- 
1.8.2

Re: [PATCH 7/7] drm/i915: Add a pipeless ivybridge configuration

[Daniel Vetter]

On Fri, Apr 05, 2013 at 01:12:45PM -0700, Ben Widawsky wrote:
> FIXME: This is based on some HW being used for a demo. We should
> probably wait until we have confirmation on the IDs before upstreaming
> this patch.
> 
> v2: Use GEN7_FEATURES (Chris)
> 
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>

Slurped in entire patch series for -next, thanks for the patches.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch