From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Daniel Vetter <daniel@ffwll.ch>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/i915: Reject fence stride=0 on gen4+
Date: Tue, 9 Apr 2013 18:08:32 +0300 [thread overview]
Message-ID: <20130409150832.GU4469@intel.com> (raw)
In-Reply-To: <20130409150118.GA2228@phenom.ffwll.local>
On Tue, Apr 09, 2013 at 05:01:18PM +0200, Daniel Vetter wrote:
> On Tue, Apr 09, 2013 at 05:46:45PM +0300, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Our checks for an invalid fence stride forgot to guard against
> > zero stride on gen4+. Fix it.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> This duplicates the tiny stride check a bit with the gen2/3 code. What
> about
>
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c
> index c807eb9..b56185f 100644
> --- a/drivers/gpu/drm/i915/i915_gem_tiling.c
> +++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
> @@ -235,6 +235,9 @@ i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode)
> }
> }
>
> + if (stride < tile_width)
> + return false;
> +
> /* 965+ just needs multiples of tile width */
> if (INTEL_INFO(dev)->gen >= 4) {
> if (stride & (tile_width - 1))
> @@ -243,9 +246,6 @@ i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode)
> }
>
> /* Pre-965 needs power of two tile widths */
> - if (stride < tile_width)
> - return false;
> -
> if (stride & (stride - 1))
> return false;
>
> instead?
Looks OK. The same idea occured to me, but only after hitting enter.
> -Daniel
>
> > ---
> > drivers/gpu/drm/i915/i915_gem_tiling.c | 2 ++
> > 1 file changed, 2 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c
> > index 139d17d..16ff6e7 100644
> > --- a/drivers/gpu/drm/i915/i915_gem_tiling.c
> > +++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
> > @@ -240,6 +240,8 @@ i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode)
> >
> > /* 965+ just needs multiples of tile width */
> > if (INTEL_INFO(dev)->gen >= 4) {
> > + if (stride < tile_width)
> > + return false;
> > if (stride & (tile_width - 1))
> > return false;
> > return true;
> > --
> > 1.8.1.5
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> +41 (0) 79 365 57 48 - http://blog.ffwll.ch
--
Ville Syrjälä
Intel OTC
next prev parent reply other threads:[~2013-04-09 15:08 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-04-09 14:46 [PATCH] drm/i915: Reject fence stride=0 on gen4+ ville.syrjala
2013-04-09 15:01 ` Daniel Vetter
2013-04-09 15:08 ` Ville Syrjälä [this message]
2013-04-09 17:09 ` [PATCH v2] " ville.syrjala
2013-04-09 17:32 ` Daniel Vetter
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