From: Paul Mackerras <paulus@samba.org>
To: Alexander Graf <agraf@suse.de>
Cc: "kvm-ppc@vger.kernel.org" <kvm-ppc@vger.kernel.org>,
"kvm@vger.kernel.org mailing list" <kvm@vger.kernel.org>
Subject: Re: [RFC PATCH 06/10] KVM: PPC: Book3S HV: Implement architecture compatibility modes for POWER8
Date: Wed, 06 Nov 2013 05:15:35 +0000 [thread overview]
Message-ID: <20131106051535.GF14842@drongo> (raw)
In-Reply-To: <E14EA3A7-AC87-4B32-97D0-2414173B867A@suse.de>
On Tue, Nov 05, 2013 at 07:06:17AM +0100, Alexander Graf wrote:
>
>
> Am 05.11.2013 um 04:53 schrieb Paul Mackerras <paulus@samba.org>:
>
> > On Mon, Nov 04, 2013 at 01:53:36PM +0100, Alexander Graf wrote:
> >>
> >> On 06.09.2013, at 05:55, Paul Mackerras <paulus@samba.org> wrote:
> >>
> >>> This allows us to select architecture 2.05 (POWER6) or 2.06 (POWER7)
> >>> compatibility modes on a POWER8 processor.
> >>>
> >>> Signed-off-by: Paul Mackerras <paulus@samba.org>
> >>> ---
> >>> arch/powerpc/include/asm/reg.h | 2 ++
> >>> arch/powerpc/kvm/book3s_hv.c | 16 +++++++++++++++-
> >>> 2 files changed, 17 insertions(+), 1 deletion(-)
> >>>
> >>> diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
> >>> index 4ca8b85..483e0a2 100644
> >>> --- a/arch/powerpc/include/asm/reg.h
> >>> +++ b/arch/powerpc/include/asm/reg.h
> >>> @@ -315,6 +315,8 @@
> >>> #define SPRN_PCR 0x152 /* Processor compatibility register */
> >>> #define PCR_VEC_DIS (1ul << (63-0)) /* Vec. disable (pre POWER8) */
> >>> #define PCR_VSX_DIS (1ul << (63-1)) /* VSX disable (pre POWER8) */
> >>> +#define PCR_TM_DIS (1ul << (63-2)) /* Trans. memory disable (POWER8) */
> >>
> >> Is this going to get used?
> >
> > Perhaps not, but I thought it worthwhile to document that the bit
> > exists.
>
> But why not? Does that mean we allow TM to be used in p7 compat mode?
No; TM is disabled if either or both of the PCR_TM_DIS and PCR_ARCH_206
bits are set.
Paul.
WARNING: multiple messages have this Message-ID (diff)
From: Paul Mackerras <paulus@samba.org>
To: Alexander Graf <agraf@suse.de>
Cc: "kvm-ppc@vger.kernel.org" <kvm-ppc@vger.kernel.org>,
"kvm@vger.kernel.org mailing list" <kvm@vger.kernel.org>
Subject: Re: [RFC PATCH 06/10] KVM: PPC: Book3S HV: Implement architecture compatibility modes for POWER8
Date: Wed, 6 Nov 2013 16:15:35 +1100 [thread overview]
Message-ID: <20131106051535.GF14842@drongo> (raw)
In-Reply-To: <E14EA3A7-AC87-4B32-97D0-2414173B867A@suse.de>
On Tue, Nov 05, 2013 at 07:06:17AM +0100, Alexander Graf wrote:
>
>
> Am 05.11.2013 um 04:53 schrieb Paul Mackerras <paulus@samba.org>:
>
> > On Mon, Nov 04, 2013 at 01:53:36PM +0100, Alexander Graf wrote:
> >>
> >> On 06.09.2013, at 05:55, Paul Mackerras <paulus@samba.org> wrote:
> >>
> >>> This allows us to select architecture 2.05 (POWER6) or 2.06 (POWER7)
> >>> compatibility modes on a POWER8 processor.
> >>>
> >>> Signed-off-by: Paul Mackerras <paulus@samba.org>
> >>> ---
> >>> arch/powerpc/include/asm/reg.h | 2 ++
> >>> arch/powerpc/kvm/book3s_hv.c | 16 +++++++++++++++-
> >>> 2 files changed, 17 insertions(+), 1 deletion(-)
> >>>
> >>> diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
> >>> index 4ca8b85..483e0a2 100644
> >>> --- a/arch/powerpc/include/asm/reg.h
> >>> +++ b/arch/powerpc/include/asm/reg.h
> >>> @@ -315,6 +315,8 @@
> >>> #define SPRN_PCR 0x152 /* Processor compatibility register */
> >>> #define PCR_VEC_DIS (1ul << (63-0)) /* Vec. disable (pre POWER8) */
> >>> #define PCR_VSX_DIS (1ul << (63-1)) /* VSX disable (pre POWER8) */
> >>> +#define PCR_TM_DIS (1ul << (63-2)) /* Trans. memory disable (POWER8) */
> >>
> >> Is this going to get used?
> >
> > Perhaps not, but I thought it worthwhile to document that the bit
> > exists.
>
> But why not? Does that mean we allow TM to be used in p7 compat mode?
No; TM is disabled if either or both of the PCR_TM_DIS and PCR_ARCH_206
bits are set.
Paul.
next prev parent reply other threads:[~2013-11-06 5:15 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-09-06 3:48 [RFC PATCH 0/10] Support POWER8 in HV KVM Paul Mackerras
2013-09-06 3:48 ` Paul Mackerras
2013-09-06 3:50 ` [RFC PATCH 01/10] KVM: PPC: Book3S HV: Align physical CPU thread numbers with virtual Paul Mackerras
2013-09-06 3:50 ` Paul Mackerras
2013-09-06 3:51 ` [RFC PATCH 02/10] KVM: PPC: Book3S HV: Don't set DABR on POWER8 Paul Mackerras
2013-09-06 3:51 ` Paul Mackerras
2013-09-06 3:51 ` [RFC PATCH 03/10] KVM: PPC: Book3S HV: Context-switch new POWER8 SPRs Paul Mackerras
2013-09-06 3:51 ` Paul Mackerras
2013-09-06 3:53 ` [RFC PATCH 04/10] KVM: PPC: Book3S HV: Flush the correct number of TLB sets on POWER8 Paul Mackerras
2013-09-06 3:53 ` Paul Mackerras
2013-09-06 3:54 ` [RFC PATCH 05/10] KVM: PPC: Book3S HV: Add handler for HV facility unavailable Paul Mackerras
2013-09-06 3:54 ` Paul Mackerras
2013-11-04 12:48 ` Alexander Graf
2013-11-04 12:48 ` Alexander Graf
2013-09-06 3:55 ` [RFC PATCH 06/10] KVM: PPC: Book3S HV: Implement architecture compatibility modes for POWER8 Paul Mackerras
2013-09-06 3:55 ` Paul Mackerras
2013-11-04 12:53 ` Alexander Graf
2013-11-04 12:53 ` Alexander Graf
2013-11-05 3:53 ` Paul Mackerras
2013-11-05 3:53 ` Paul Mackerras
2013-11-05 6:06 ` Alexander Graf
2013-11-05 6:06 ` Alexander Graf
2013-11-06 5:15 ` Paul Mackerras [this message]
2013-11-06 5:15 ` Paul Mackerras
2013-09-06 3:58 ` [RFC PATCH 07/10] KVM: PPC: Book3S HV: Consolidate code that checks reason for wake from nap Paul Mackerras
2013-09-06 3:58 ` Paul Mackerras
2013-09-06 3:58 ` [RFC PATCH 08/10] KVM: PPC: Book3S HV: Handle guest using doorbells for IPIs Paul Mackerras
2013-09-06 3:58 ` Paul Mackerras
2013-09-06 3:59 ` [RFC PATCH 09/10] KVM: PPC: Book3S HV: Handle new LPCR bits on POWER8 Paul Mackerras
2013-09-06 3:59 ` Paul Mackerras
2013-09-06 4:00 ` [RFC PATCH 10/10] KVM: PPC: Book3S HV: Prepare for host using hypervisor doorbells Paul Mackerras
2013-09-06 4:00 ` Paul Mackerras
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