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From: Paul Walmsley <pwalmsley-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
To: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
Cc: Thierry Reding
	<thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>,
	Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
Subject: [PATCH 2/6] ARM: tegra114: fuse: add DFLL FCPU minimum voltage override test function
Date: Thu, 19 Dec 2013 04:36:56 -0800	[thread overview]
Message-ID: <20131219123652.3226.98741.stgit@tamien> (raw)
In-Reply-To: <20131219122857.3226.42830.stgit@tamien>

Add a function to test the internal Tegra114 chip fuse that indicates
whether the VDD_CPU lower voltage limit for the fast CPU cluster
should be overridden.

Signed-off-by: Paul Walmsley <pwalmsley-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
Cc: Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
Cc: Thierry Reding <thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
 arch/arm/mach-tegra/fuse.c |   26 ++++++++++++++++++++++++++
 include/linux/tegra-soc.h  |    2 ++
 2 files changed, 28 insertions(+)

diff --git a/arch/arm/mach-tegra/fuse.c b/arch/arm/mach-tegra/fuse.c
index e3ca8abe858f..42477aa1b7e9 100644
--- a/arch/arm/mach-tegra/fuse.c
+++ b/arch/arm/mach-tegra/fuse.c
@@ -47,6 +47,15 @@
 #define TEGRA20_FUSE_SPARE_BIT		0x200
 #define TEGRA30_FUSE_SPARE_BIT		0x244
 
+/*
+ * TEGRA114_SPARE_FUSE_VDD_CPU_OVERRIDE: Spare eFuse ID that indicates
+ * whether the minimum VDD_CPU voltage level that the DFLL is
+ * characterized for should be overridden to 900mVdc.  If unset, the
+ * voltage shouldn't be overridden - it will be whatever has been
+ * selected by the CPU Speedo and process IDs.
+ */
+#define TEGRA114_SPARE_FUSE_VDD_CPU_OVERRIDE		61
+
 int tegra_sku_id;
 int tegra_cpu_process_id;
 int tegra_core_process_id;
@@ -265,3 +274,20 @@ int tegra_get_cpu_speedo_id(void)
 	return tegra_cpu_speedo_id;
 }
 EXPORT_SYMBOL(tegra_get_cpu_speedo_id);
+
+/**
+ * tegra114_fuse_read_min_vdd_cpu_override - override DFLL VDD_CPU minimum?
+ *
+ * Returns true if the minimum VDD_CPU voltage level that the DFLL is
+ * characterized for is 900mVdc.  If false, the minimum voltage should
+ * be whatever has been selected by the CPU Speedo and process IDs.
+ */
+bool tegra114_fuse_read_min_vdd_cpu_override(void)
+{
+	if (tegra_chip_id != TEGRA114)
+		return -EINVAL;
+
+	return tegra_spare_fuse(TEGRA114_SPARE_FUSE_VDD_CPU_OVERRIDE) ? true :
+		false;
+}
+EXPORT_SYMBOL(tegra114_fuse_read_min_vdd_cpu_override);
diff --git a/include/linux/tegra-soc.h b/include/linux/tegra-soc.h
index ec856fdf2ce7..fe2ab641555e 100644
--- a/include/linux/tegra-soc.h
+++ b/include/linux/tegra-soc.h
@@ -21,4 +21,6 @@ u32 tegra_read_chipid(void);
 int tegra_get_cpu_process_id(void);
 int tegra_get_cpu_speedo_id(void);
 
+bool tegra114_fuse_read_min_vdd_cpu_override(void);
+
 #endif /* __LINUX_TEGRA_SOC_H_ */

WARNING: multiple messages have this Message-ID (diff)
From: pwalmsley@nvidia.com (Paul Walmsley)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 2/6] ARM: tegra114: fuse: add DFLL FCPU minimum voltage override test function
Date: Thu, 19 Dec 2013 04:36:56 -0800	[thread overview]
Message-ID: <20131219123652.3226.98741.stgit@tamien> (raw)
In-Reply-To: <20131219122857.3226.42830.stgit@tamien>

Add a function to test the internal Tegra114 chip fuse that indicates
whether the VDD_CPU lower voltage limit for the fast CPU cluster
should be overridden.

Signed-off-by: Paul Walmsley <pwalmsley@nvidia.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Thierry Reding <thierry.reding@gmail.com>
---
 arch/arm/mach-tegra/fuse.c |   26 ++++++++++++++++++++++++++
 include/linux/tegra-soc.h  |    2 ++
 2 files changed, 28 insertions(+)

diff --git a/arch/arm/mach-tegra/fuse.c b/arch/arm/mach-tegra/fuse.c
index e3ca8abe858f..42477aa1b7e9 100644
--- a/arch/arm/mach-tegra/fuse.c
+++ b/arch/arm/mach-tegra/fuse.c
@@ -47,6 +47,15 @@
 #define TEGRA20_FUSE_SPARE_BIT		0x200
 #define TEGRA30_FUSE_SPARE_BIT		0x244
 
+/*
+ * TEGRA114_SPARE_FUSE_VDD_CPU_OVERRIDE: Spare eFuse ID that indicates
+ * whether the minimum VDD_CPU voltage level that the DFLL is
+ * characterized for should be overridden to 900mVdc.  If unset, the
+ * voltage shouldn't be overridden - it will be whatever has been
+ * selected by the CPU Speedo and process IDs.
+ */
+#define TEGRA114_SPARE_FUSE_VDD_CPU_OVERRIDE		61
+
 int tegra_sku_id;
 int tegra_cpu_process_id;
 int tegra_core_process_id;
@@ -265,3 +274,20 @@ int tegra_get_cpu_speedo_id(void)
 	return tegra_cpu_speedo_id;
 }
 EXPORT_SYMBOL(tegra_get_cpu_speedo_id);
+
+/**
+ * tegra114_fuse_read_min_vdd_cpu_override - override DFLL VDD_CPU minimum?
+ *
+ * Returns true if the minimum VDD_CPU voltage level that the DFLL is
+ * characterized for is 900mVdc.  If false, the minimum voltage should
+ * be whatever has been selected by the CPU Speedo and process IDs.
+ */
+bool tegra114_fuse_read_min_vdd_cpu_override(void)
+{
+	if (tegra_chip_id != TEGRA114)
+		return -EINVAL;
+
+	return tegra_spare_fuse(TEGRA114_SPARE_FUSE_VDD_CPU_OVERRIDE) ? true :
+		false;
+}
+EXPORT_SYMBOL(tegra114_fuse_read_min_vdd_cpu_override);
diff --git a/include/linux/tegra-soc.h b/include/linux/tegra-soc.h
index ec856fdf2ce7..fe2ab641555e 100644
--- a/include/linux/tegra-soc.h
+++ b/include/linux/tegra-soc.h
@@ -21,4 +21,6 @@ u32 tegra_read_chipid(void);
 int tegra_get_cpu_process_id(void);
 int tegra_get_cpu_speedo_id(void);
 
+bool tegra114_fuse_read_min_vdd_cpu_override(void);
+
 #endif /* __LINUX_TEGRA_SOC_H_ */

  parent reply	other threads:[~2013-12-19 12:36 UTC|newest]

Thread overview: 38+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-12-19 12:36 [PATCH 0/6] clk: tegra: add basic support for the DFLL clocksource Paul Walmsley
2013-12-19 12:36 ` Paul Walmsley
2013-12-19 12:36 ` [PATCH 1/6] ARM: tegra: fuse: add functions to read speedo ID and process ID Paul Walmsley
2013-12-19 12:36   ` Paul Walmsley
2013-12-19 23:09   ` Stephen Warren
2013-12-19 23:09     ` Stephen Warren
2013-12-19 12:36 ` Paul Walmsley [this message]
2013-12-19 12:36   ` [PATCH 2/6] ARM: tegra114: fuse: add DFLL FCPU minimum voltage override test function Paul Walmsley
2013-12-19 23:12   ` Stephen Warren
2013-12-19 23:12     ` Stephen Warren
2013-12-19 12:37 ` [PATCH 3/6] clk: tegra: add library for the DFLL clocksource (open-loop mode) Paul Walmsley
2013-12-19 12:37   ` Paul Walmsley
2013-12-19 23:57   ` Stephen Warren
2013-12-19 23:57     ` Stephen Warren
2013-12-19 12:49 ` [PATCH 4/6] ARM: DTS: tegra: add the DFLL IP block to the T114 SoC file Paul Walmsley
2013-12-19 12:49   ` Paul Walmsley
2013-12-20  0:05   ` Stephen Warren
2013-12-20  0:05     ` Stephen Warren
     [not found]     ` <52B389CD.8010004-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
2014-01-14  6:27       ` Paul Walmsley
2014-01-14  6:27         ` Paul Walmsley
2014-01-14  6:32         ` Paul Walmsley
2014-01-14  6:32           ` Paul Walmsley
2014-01-15 19:50         ` Gerhard Sittig
2014-01-15 19:50           ` Gerhard Sittig
     [not found]           ` <20140115195025.GU20094-kDjWylLy9wD0K7fsECOQyeGNnDKD8DIp@public.gmane.org>
2014-01-15 20:09             ` Paul Walmsley
2014-01-15 20:09               ` Paul Walmsley
     [not found]     ` <52D4D314.3000208@nvidia.com>
     [not found]       ` <52D4D314.3000208-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2014-01-14 17:43         ` Stephen Warren
2014-01-14 17:43           ` Stephen Warren
2013-12-19 12:49 ` [PATCH 5/6] ARM: DTS: tegra: add DFLL integration to the Dalmore DTS file Paul Walmsley
2013-12-19 12:49   ` Paul Walmsley
2013-12-20  0:10   ` Stephen Warren
2013-12-20  0:10     ` Stephen Warren
     [not found]     ` <52B38AE9.2030209-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
2014-01-14  6:36       ` Paul Walmsley
2014-01-14  6:36         ` Paul Walmsley
2013-12-19 12:49 ` [PATCH 6/6] clk: tegra: add Tegra114 FCPU DFLL clocksource platform driver Paul Walmsley
2013-12-19 12:49   ` Paul Walmsley
2013-12-20  0:18   ` Stephen Warren
2013-12-20  0:18     ` Stephen Warren

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