From: Ingo Molnar <mingo@kernel.org>
To: Mel Gorman <mgorman@suse.de>
Cc: Linus Torvalds <torvalds@linux-foundation.org>,
Alex Shi <alex.shi@linaro.org>,
Thomas Gleixner <tglx@linutronix.de>,
Andrew Morton <akpm@linux-foundation.org>,
Fengguang Wu <fengguang.wu@intel.com>,
H Peter Anvin <hpa@zytor.com>, Linux-X86 <x86@kernel.org>,
Linux-MM <linux-mm@kvack.org>,
LKML <linux-kernel@vger.kernel.org>,
Peter Zijlstra <a.p.zijlstra@chello.nl>
Subject: Re: [PATCH 0/4] Fix ebizzy performance regression due to X86 TLB range flush v2
Date: Fri, 20 Dec 2013 13:20:19 +0100 [thread overview]
Message-ID: <20131220122019.GA24479@gmail.com> (raw)
In-Reply-To: <20131220115854.GA11295@suse.de>
* Mel Gorman <mgorman@suse.de> wrote:
> tlb_flushall_shift == -1 Always use flush all
> tlb_flushall_shift == 1 Aggressively use individual flushes
> tlb_flushall_shift == 6 Conservatively use individual flushes
>
> IvyBridge was too aggressive using individual flushes and my patch
> makes it less aggressive.
>
> Intel's code for this currently looks like
>
> switch ((c->x86 << 8) + c->x86_model) {
> case 0x60f: /* original 65 nm celeron/pentium/core2/xeon, "Merom"/"Conroe" */
> case 0x616: /* single-core 65 nm celeron/core2solo "Merom-L"/"Conroe-L" */
> case 0x617: /* current 45 nm celeron/core2/xeon "Penryn"/"Wolfdale" */
> case 0x61d: /* six-core 45 nm xeon "Dunnington" */
> tlb_flushall_shift = -1;
> break;
> case 0x61a: /* 45 nm nehalem, "Bloomfield" */
> case 0x61e: /* 45 nm nehalem, "Lynnfield" */
> case 0x625: /* 32 nm nehalem, "Clarkdale" */
> case 0x62c: /* 32 nm nehalem, "Gulftown" */
> case 0x62e: /* 45 nm nehalem-ex, "Beckton" */
> case 0x62f: /* 32 nm Xeon E7 */
> tlb_flushall_shift = 6;
> break;
> case 0x62a: /* SandyBridge */
> case 0x62d: /* SandyBridge, "Romely-EP" */
> tlb_flushall_shift = 5;
> break;
> case 0x63a: /* Ivybridge */
> tlb_flushall_shift = 2;
> break;
> default:
> tlb_flushall_shift = 6;
> }
>
> That default shift of "6" is already conservative which is why I
> don't think we need to change anything there. AMD is slightly more
> aggressive in their choices but not enough to panic.
Lets face it, the per model tunings are most likely crap: the only
place where it significantly deviated from '6' was Ivybridge - and
there it was causing a regression.
With your patch we'll have 6 everywhere, except on SandyBridge where
it's slightly more agressive at 5 - which is probably noise.
So my argument is that we should use '6' _everywhere_ and do away with
the pretense that we do per model tunings...
Thanks,
Ingo
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WARNING: multiple messages have this Message-ID (diff)
From: Ingo Molnar <mingo@kernel.org>
To: Mel Gorman <mgorman@suse.de>
Cc: Linus Torvalds <torvalds@linux-foundation.org>,
Alex Shi <alex.shi@linaro.org>,
Thomas Gleixner <tglx@linutronix.de>,
Andrew Morton <akpm@linux-foundation.org>,
Fengguang Wu <fengguang.wu@intel.com>,
H Peter Anvin <hpa@zytor.com>, Linux-X86 <x86@kernel.org>,
Linux-MM <linux-mm@kvack.org>,
LKML <linux-kernel@vger.kernel.org>,
Peter Zijlstra <a.p.zijlstra@chello.nl>
Subject: Re: [PATCH 0/4] Fix ebizzy performance regression due to X86 TLB range flush v2
Date: Fri, 20 Dec 2013 13:20:19 +0100 [thread overview]
Message-ID: <20131220122019.GA24479@gmail.com> (raw)
In-Reply-To: <20131220115854.GA11295@suse.de>
* Mel Gorman <mgorman@suse.de> wrote:
> tlb_flushall_shift == -1 Always use flush all
> tlb_flushall_shift == 1 Aggressively use individual flushes
> tlb_flushall_shift == 6 Conservatively use individual flushes
>
> IvyBridge was too aggressive using individual flushes and my patch
> makes it less aggressive.
>
> Intel's code for this currently looks like
>
> switch ((c->x86 << 8) + c->x86_model) {
> case 0x60f: /* original 65 nm celeron/pentium/core2/xeon, "Merom"/"Conroe" */
> case 0x616: /* single-core 65 nm celeron/core2solo "Merom-L"/"Conroe-L" */
> case 0x617: /* current 45 nm celeron/core2/xeon "Penryn"/"Wolfdale" */
> case 0x61d: /* six-core 45 nm xeon "Dunnington" */
> tlb_flushall_shift = -1;
> break;
> case 0x61a: /* 45 nm nehalem, "Bloomfield" */
> case 0x61e: /* 45 nm nehalem, "Lynnfield" */
> case 0x625: /* 32 nm nehalem, "Clarkdale" */
> case 0x62c: /* 32 nm nehalem, "Gulftown" */
> case 0x62e: /* 45 nm nehalem-ex, "Beckton" */
> case 0x62f: /* 32 nm Xeon E7 */
> tlb_flushall_shift = 6;
> break;
> case 0x62a: /* SandyBridge */
> case 0x62d: /* SandyBridge, "Romely-EP" */
> tlb_flushall_shift = 5;
> break;
> case 0x63a: /* Ivybridge */
> tlb_flushall_shift = 2;
> break;
> default:
> tlb_flushall_shift = 6;
> }
>
> That default shift of "6" is already conservative which is why I
> don't think we need to change anything there. AMD is slightly more
> aggressive in their choices but not enough to panic.
Lets face it, the per model tunings are most likely crap: the only
place where it significantly deviated from '6' was Ivybridge - and
there it was causing a regression.
With your patch we'll have 6 everywhere, except on SandyBridge where
it's slightly more agressive at 5 - which is probably noise.
So my argument is that we should use '6' _everywhere_ and do away with
the pretense that we do per model tunings...
Thanks,
Ingo
next prev parent reply other threads:[~2013-12-20 12:20 UTC|newest]
Thread overview: 71+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-12-13 20:01 [PATCH 0/4] Fix ebizzy performance regression due to X86 TLB range flush v2 Mel Gorman
2013-12-13 20:01 ` Mel Gorman
2013-12-13 20:01 ` [PATCH 1/4] x86: mm: Clean up inconsistencies when flushing TLB ranges Mel Gorman
2013-12-13 20:01 ` Mel Gorman
2013-12-13 20:01 ` [PATCH 2/4] x86: mm: Account for TLB flushes only when debugging Mel Gorman
2013-12-13 20:01 ` Mel Gorman
2013-12-13 20:01 ` [PATCH 3/4] x86: mm: Change tlb_flushall_shift for IvyBridge Mel Gorman
2013-12-13 20:01 ` Mel Gorman
2013-12-13 20:01 ` [PATCH 4/4] x86: mm: Eliminate redundant page table walk during TLB range flushing Mel Gorman
2013-12-13 20:01 ` Mel Gorman
2013-12-13 21:16 ` [PATCH 0/4] Fix ebizzy performance regression due to X86 TLB range flush v2 Linus Torvalds
2013-12-13 21:16 ` Linus Torvalds
2013-12-13 22:38 ` H. Peter Anvin
2013-12-13 22:38 ` H. Peter Anvin
2013-12-16 10:39 ` Mel Gorman
2013-12-16 10:39 ` Mel Gorman
2013-12-16 17:17 ` Linus Torvalds
2013-12-16 17:17 ` Linus Torvalds
2013-12-17 9:55 ` Mel Gorman
2013-12-17 9:55 ` Mel Gorman
2013-12-15 15:55 ` Mel Gorman
2013-12-15 15:55 ` Mel Gorman
2013-12-15 16:17 ` Mel Gorman
2013-12-15 16:17 ` Mel Gorman
2013-12-15 18:34 ` Linus Torvalds
2013-12-15 18:34 ` Linus Torvalds
2013-12-16 11:16 ` Mel Gorman
2013-12-16 11:16 ` Mel Gorman
2013-12-16 10:24 ` Ingo Molnar
2013-12-16 10:24 ` Ingo Molnar
2013-12-16 12:59 ` Mel Gorman
2013-12-16 12:59 ` Mel Gorman
2013-12-16 13:44 ` Ingo Molnar
2013-12-16 13:44 ` Ingo Molnar
2013-12-17 9:21 ` Mel Gorman
2013-12-17 9:21 ` Mel Gorman
2013-12-17 9:26 ` Peter Zijlstra
2013-12-17 9:26 ` Peter Zijlstra
2013-12-17 11:00 ` Ingo Molnar
2013-12-17 11:00 ` Ingo Molnar
2013-12-17 14:32 ` Mel Gorman
2013-12-17 14:32 ` Mel Gorman
2013-12-17 14:42 ` Ingo Molnar
2013-12-17 14:42 ` Ingo Molnar
2013-12-17 17:54 ` Mel Gorman
2013-12-17 17:54 ` Mel Gorman
2013-12-18 10:24 ` Ingo Molnar
2013-12-18 10:24 ` Ingo Molnar
2013-12-19 14:24 ` Mel Gorman
2013-12-19 14:24 ` Mel Gorman
2013-12-19 16:49 ` Ingo Molnar
2013-12-19 16:49 ` Ingo Molnar
2013-12-20 11:13 ` Mel Gorman
2013-12-20 11:13 ` Mel Gorman
2013-12-20 11:18 ` Ingo Molnar
2013-12-20 11:18 ` Ingo Molnar
2013-12-20 12:00 ` Mel Gorman
2013-12-20 12:00 ` Mel Gorman
2013-12-20 12:20 ` Ingo Molnar [this message]
2013-12-20 12:20 ` Ingo Molnar
2013-12-20 13:55 ` Mel Gorman
2013-12-20 13:55 ` Mel Gorman
2013-12-18 10:32 ` [tip:sched/core] sched: Assign correct scheduling domain to ' sd_llc' tip-bot for Mel Gorman
2013-12-18 7:28 ` [PATCH 0/4] Fix ebizzy performance regression due to X86 TLB range flush v2 Fengguang Wu
2013-12-18 7:28 ` Fengguang Wu
2013-12-19 14:34 ` Mel Gorman
2013-12-19 14:34 ` Mel Gorman
2013-12-20 15:51 ` Fengguang Wu
2013-12-20 16:44 ` Mel Gorman
2013-12-20 16:44 ` Mel Gorman
2013-12-21 15:49 ` Fengguang Wu
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