Re: [PATCH] x86, tsc: Add missing Baytrail frequency to the table

[Mika Westerberg <mika.westerberg@linux.intel.com>]

On Thu, Jan 23, 2014 at 03:09:12PM +0000, One Thousand Gnomes wrote:
> On Thu, 23 Jan 2014 13:04:03 +0200
> Mika Westerberg <mika.westerberg@linux.intel.com> wrote:
> 
> > Baytrail is based on Silvermont core so MSR_FSB_FREQ[2:0] == 0 means that
> > the CPU reference clock runs at 83.3MHz. Without this we crash a bit later
> > with backtrace looking like:
> 
> Would it not be wise to also make the code robust against future failures
> of this kind and at least bitch rather than divide by 0 ?

Yes, it makes sense. I wasn't sure how to do that properly, though.

The following patch seems to work in that case.

diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c
index a3acbac2ee72..1e54deb56b33 100644
--- a/arch/x86/kernel/tsc.c
+++ b/arch/x86/kernel/tsc.c
@@ -655,10 +655,11 @@ unsigned long native_calibrate_tsc(void)
 	local_irq_save(flags);
 	i = try_msr_calibrate_tsc(&fast_calibrate);
 	local_irq_restore(flags);
-	if (i >= 0) {
-		if (i == 0)
-			pr_warn("Fast TSC calibration using MSR failed\n");
+	if (i > 0) {
 		return fast_calibrate;
+	} else if (i == 0) {
+		pr_warn("Fast TSC calibration using MSR failed\n");
+		/* Continue with the normal calibration */
 	}
 
 	local_irq_save(flags);