Re: [PATCH v2] x86, tsc: Add missing Baytrail frequency to the table

[Bin Gao <bin.gao@linux.intel.com>]

> diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c index a3acbac2ee72$
> --- a/arch/x86/kernel/tsc.c
> +++ b/arch/x86/kernel/tsc.c
> @@ -655,10 +655,11 @@ unsigned long native_calibrate_tsc(void)
>       local_irq_save(flags);
>       i = try_msr_calibrate_tsc(&fast_calibrate);
>       local_irq_restore(flags);
> -     if (i >= 0) {
> -             if (i == 0)
> -                     pr_warn("Fast TSC calibration using MSR failed\n");
> +     if (i > 0) {
>               return fast_calibrate;
> +     } else if (i == 0) {
> +             pr_warn("Fast TSC calibration using MSR failed\n");
> +             /* Continue with the normal calibration */
>       }
>
>       local_irq_save(flags);

The original design is to avoid trying PIC because touching PIC on
a non-PIC SoC will simply cause system hang. Returning 0 will cause
kernel to mark TSC unstable(rating 0). Since PM timer and HPET are
typically not available on non-PIC SoC, kernal falls back to jiffies
as clock source. Developers will start looking into the TSC clibrating
failure once they notice the jiffies clock source.

>[<ffffffff810aecb0>] clockevents_config_and_register+0x20/0x30
>[<ffffffff81030168>] setup_APIC_timer+0xc8/0xd0
>[<ffffffff81d1104f>] setup_boot_APIC_clock+0x4cc/0x4d8
>[<ffffffff81d0f5de>] native_smp_prepare_cpus+0x3dd/0x3f0
>[<ffffffff81d02ee9>] kernel_init_freeable+0xc3/0x205
>[<ffffffff8177c910>] ? rest_init+0x90/0x90
>[<ffffffff8177c91e>] kernel_init+0xe/0x120
>[<ffffffff8178deec>] ret_from_fork+0x7c/0xb0
>[<ffffffff8177c910>] ? rest_init+0x90/0x90

This is because kernel is trying to use tsc-deadline mode for lapic
timer. I think the right fix is to unset X86_FEATURE_TSC_DEADLINE_TIMER
when try_msr_calibrate_tsc() returns 0.