From: Wolfram Sang <wsa-z923LK4zBo2bacvFa/9K2g@public.gmane.org>
To: Chew Chiau Ee <chiau.ee.chew-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
Cc: Mika Westerberg
<mika.westerberg-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>,
linux-i2c-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Subject: Re: [PATCH 2/2] i2c: designware-pci: set ideal HCNT, LCNT and SDA hold time value
Date: Sun, 9 Mar 2014 10:03:39 +0100 [thread overview]
Message-ID: <20140309090339.GB4695@katana> (raw)
In-Reply-To: <1394201571-11681-3-git-send-email-chiau.ee.chew-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
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On Fri, Mar 07, 2014 at 10:12:51PM +0800, Chew Chiau Ee wrote:
> From: Chew, Chiau Ee <chiau.ee.chew-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
>
> On Intel BayTrail, there was case whereby the resulting fast mode
> bus speed becomes slower (~20% slower compared to expected speed)
> if using the HCNT/LCNT calculated in the core layer. Thus, this
> patch is added to allow pci glue layer to pass in optimal
> HCNT/LCNT/SDA hold time values to core layer since the core
> layer supports cofigurable HCNT/LCNT/SDA hold time values now.
>
> Signed-off-by: Chew, Chiau Ee <chiau.ee.chew-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
Can you make use of those instead?
u32 sda_falling_time;
u32 scl_falling_time;
This is more consistent with using sda_hold_time and lets them have a
common (and more readable) unit.
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WARNING: multiple messages have this Message-ID (diff)
From: Wolfram Sang <wsa@the-dreams.de>
To: Chew Chiau Ee <chiau.ee.chew@intel.com>
Cc: Mika Westerberg <mika.westerberg@linux.intel.com>,
linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 2/2] i2c: designware-pci: set ideal HCNT, LCNT and SDA hold time value
Date: Sun, 9 Mar 2014 10:03:39 +0100 [thread overview]
Message-ID: <20140309090339.GB4695@katana> (raw)
In-Reply-To: <1394201571-11681-3-git-send-email-chiau.ee.chew@intel.com>
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On Fri, Mar 07, 2014 at 10:12:51PM +0800, Chew Chiau Ee wrote:
> From: Chew, Chiau Ee <chiau.ee.chew@intel.com>
>
> On Intel BayTrail, there was case whereby the resulting fast mode
> bus speed becomes slower (~20% slower compared to expected speed)
> if using the HCNT/LCNT calculated in the core layer. Thus, this
> patch is added to allow pci glue layer to pass in optimal
> HCNT/LCNT/SDA hold time values to core layer since the core
> layer supports cofigurable HCNT/LCNT/SDA hold time values now.
>
> Signed-off-by: Chew, Chiau Ee <chiau.ee.chew@intel.com>
Can you make use of those instead?
u32 sda_falling_time;
u32 scl_falling_time;
This is more consistent with using sda_hold_time and lets them have a
common (and more readable) unit.
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next prev parent reply other threads:[~2014-03-09 9:03 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-03-07 14:12 [PATCH 0/2] i2c: designware-pci: extra features for PCI mode LPSS I2C Chew Chiau Ee
2014-03-07 14:12 ` Chew Chiau Ee
2014-03-07 14:12 ` [PATCH 1/2] i2c: designware-pci: add 10-bit addressing mode functionality for BYT I2C Chew Chiau Ee
[not found] ` <1394201571-11681-2-git-send-email-chiau.ee.chew-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
2014-03-09 8:53 ` Wolfram Sang
2014-03-09 8:53 ` Wolfram Sang
2014-03-10 10:12 ` Chew, Chiau Ee
2014-03-10 10:12 ` Chew, Chiau Ee
[not found] ` <604BF5F4C5D71041942BC7E84ED659EA0155D56E-j2khPEwRog1zLEkEFCSWIbfspsVTdybXVpNB7YpNyf8@public.gmane.org>
2014-03-10 15:16 ` Wolfram Sang
2014-03-10 15:16 ` Wolfram Sang
2014-03-07 14:12 ` [PATCH 2/2] i2c: designware-pci: set ideal HCNT, LCNT and SDA hold time value Chew Chiau Ee
[not found] ` <1394201571-11681-3-git-send-email-chiau.ee.chew-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
2014-03-09 9:03 ` Wolfram Sang [this message]
2014-03-09 9:03 ` Wolfram Sang
2014-03-10 11:34 ` Chew, Chiau Ee
2014-03-10 11:34 ` Chew, Chiau Ee
2014-03-10 15:15 ` Wolfram Sang
2014-03-10 15:21 ` Wolfram Sang
2014-03-10 15:21 ` Wolfram Sang
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