From: Peter De Schrijver <pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
To: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
Cc: Mike Turquette
<mturquette-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>,
Prashant Gaikwad
<pgaikwad-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>,
Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>,
"linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org"
<linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
"linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org"
<linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>
Subject: Re: [PATCH v2 1/3] clk: tegra: Fix PLLE programming
Date: Mon, 7 Apr 2014 17:26:20 +0300 [thread overview]
Message-ID: <20140407142620.GA30476@tbergstrom-lnx.Nvidia.com> (raw)
In-Reply-To: <1396619715-15524-1-git-send-email-treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
On Fri, Apr 04, 2014 at 03:55:13PM +0200, Thierry Reding wrote:
> PLLE has M, N and P divider shift and width parameters that differ from
> the defaults. Furthermore, when clearing the M, N and P divider fields
> the corresponding masks were never shifted, thereby clearing only the
> lowest bits of the register. This lead to a situation where the PLLE
> programming would only work if the register hadn't been touched before.
>
Will take this into tegra-clk-next. Mike, given that this is bug fix for
a feature which is supposed to work, I think it's appropriate to try to get
this into 3.15 still. I will make a pull-request on 3.15-rc1 as soon as it
appears.
Cheers,
Peter.
WARNING: multiple messages have this Message-ID (diff)
From: Peter De Schrijver <pdeschrijver@nvidia.com>
To: Thierry Reding <treding@nvidia.com>
Cc: Mike Turquette <mturquette@linaro.org>,
Prashant Gaikwad <pgaikwad@nvidia.com>,
Stephen Warren <swarren@wwwdotorg.org>,
"linux-tegra@vger.kernel.org" <linux-tegra@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v2 1/3] clk: tegra: Fix PLLE programming
Date: Mon, 7 Apr 2014 17:26:20 +0300 [thread overview]
Message-ID: <20140407142620.GA30476@tbergstrom-lnx.Nvidia.com> (raw)
In-Reply-To: <1396619715-15524-1-git-send-email-treding@nvidia.com>
On Fri, Apr 04, 2014 at 03:55:13PM +0200, Thierry Reding wrote:
> PLLE has M, N and P divider shift and width parameters that differ from
> the defaults. Furthermore, when clearing the M, N and P divider fields
> the corresponding masks were never shifted, thereby clearing only the
> lowest bits of the register. This lead to a situation where the PLLE
> programming would only work if the register hadn't been touched before.
>
Will take this into tegra-clk-next. Mike, given that this is bug fix for
a feature which is supposed to work, I think it's appropriate to try to get
this into 3.15 still. I will make a pull-request on 3.15-rc1 as soon as it
appears.
Cheers,
Peter.
next prev parent reply other threads:[~2014-04-07 14:26 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-04-04 13:55 [PATCH v2 1/3] clk: tegra: Fix PLLE programming Thierry Reding
2014-04-04 13:55 ` Thierry Reding
2014-04-04 13:55 ` [PATCH v2 2/3] clk: tegra: Introduce divider mask and shift helpers Thierry Reding
2014-04-04 13:55 ` Thierry Reding
[not found] ` <1396619715-15524-1-git-send-email-treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2014-04-04 13:55 ` [PATCH v2 3/3] clk: tegra: Fix enabling of PLLE Thierry Reding
2014-04-04 13:55 ` Thierry Reding
2014-04-04 15:55 ` [PATCH v2 1/3] clk: tegra: Fix PLLE programming Stephen Warren
2014-04-04 15:55 ` Stephen Warren
2014-04-07 14:26 ` Peter De Schrijver [this message]
2014-04-07 14:26 ` Peter De Schrijver
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