From: Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
To: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>,
Mike Turquette
<mturquette-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>,
Peter De Schrijver
<pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>,
Prashant Gaikwad
<pgaikwad-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Subject: Re: [PATCH v2 1/3] clk: tegra: Fix PLLE programming
Date: Fri, 04 Apr 2014 09:55:51 -0600 [thread overview]
Message-ID: <533ED607.1080700@wwwdotorg.org> (raw)
In-Reply-To: <1396619715-15524-1-git-send-email-treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
On 04/04/2014 07:55 AM, Thierry Reding wrote:
> PLLE has M, N and P divider shift and width parameters that differ from
> the defaults. Furthermore, when clearing the M, N and P divider fields
> the corresponding masks were never shifted, thereby clearing only the
> lowest bits of the register. This lead to a situation where the PLLE
> programming would only work if the register hadn't been touched before.
The series,
Acked-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
(I might have squashed patches 1 and 2 together, but no matter)
I expect these patches should be CC: stable when applied?
WARNING: multiple messages have this Message-ID (diff)
From: Stephen Warren <swarren@wwwdotorg.org>
To: Thierry Reding <treding@nvidia.com>,
Mike Turquette <mturquette@linaro.org>,
Peter De Schrijver <pdeschrijver@nvidia.com>,
Prashant Gaikwad <pgaikwad@nvidia.com>
Cc: linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 1/3] clk: tegra: Fix PLLE programming
Date: Fri, 04 Apr 2014 09:55:51 -0600 [thread overview]
Message-ID: <533ED607.1080700@wwwdotorg.org> (raw)
In-Reply-To: <1396619715-15524-1-git-send-email-treding@nvidia.com>
On 04/04/2014 07:55 AM, Thierry Reding wrote:
> PLLE has M, N and P divider shift and width parameters that differ from
> the defaults. Furthermore, when clearing the M, N and P divider fields
> the corresponding masks were never shifted, thereby clearing only the
> lowest bits of the register. This lead to a situation where the PLLE
> programming would only work if the register hadn't been touched before.
The series,
Acked-by: Stephen Warren <swarren@nvidia.com>
(I might have squashed patches 1 and 2 together, but no matter)
I expect these patches should be CC: stable when applied?
next prev parent reply other threads:[~2014-04-04 15:55 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-04-04 13:55 [PATCH v2 1/3] clk: tegra: Fix PLLE programming Thierry Reding
2014-04-04 13:55 ` Thierry Reding
2014-04-04 13:55 ` [PATCH v2 2/3] clk: tegra: Introduce divider mask and shift helpers Thierry Reding
2014-04-04 13:55 ` Thierry Reding
[not found] ` <1396619715-15524-1-git-send-email-treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2014-04-04 13:55 ` [PATCH v2 3/3] clk: tegra: Fix enabling of PLLE Thierry Reding
2014-04-04 13:55 ` Thierry Reding
2014-04-04 15:55 ` Stephen Warren [this message]
2014-04-04 15:55 ` [PATCH v2 1/3] clk: tegra: Fix PLLE programming Stephen Warren
2014-04-07 14:26 ` Peter De Schrijver
2014-04-07 14:26 ` Peter De Schrijver
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