From: Richard Cochran <richardcochran-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
To: George Cherian <george.cherian-l0cyMroinI0@public.gmane.org>
Cc: netdev-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
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Subject: Re: [PATCH 4/6] drivers: net: cpsw: Enable Annexe F Time sync
Date: Mon, 28 Apr 2014 09:55:31 +0200 [thread overview]
Message-ID: <20140428075530.GA8371@netboy> (raw)
In-Reply-To: <1398658225-25873-5-git-send-email-george.cherian-l0cyMroinI0@public.gmane.org>
On Mon, Apr 28, 2014 at 09:40:23AM +0530, George Cherian wrote:
> Enable the Annex F Time Sync explicitly for DRA7x and AM4372.
> With this enabled the L2 PTP is working.
L2 works fine without this bit. If this is needed for V3 hardware,
then it should have its own code variant.
> while at that rename TS_BIT8 to TS_TTL_NONZERO
Is this bit finally documented for am335x?
Thanks,
Richard
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WARNING: multiple messages have this Message-ID (diff)
From: richardcochran@gmail.com (Richard Cochran)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 4/6] drivers: net: cpsw: Enable Annexe F Time sync
Date: Mon, 28 Apr 2014 09:55:31 +0200 [thread overview]
Message-ID: <20140428075530.GA8371@netboy> (raw)
In-Reply-To: <1398658225-25873-5-git-send-email-george.cherian@ti.com>
On Mon, Apr 28, 2014 at 09:40:23AM +0530, George Cherian wrote:
> Enable the Annex F Time Sync explicitly for DRA7x and AM4372.
> With this enabled the L2 PTP is working.
L2 works fine without this bit. If this is needed for V3 hardware,
then it should have its own code variant.
> while at that rename TS_BIT8 to TS_TTL_NONZERO
Is this bit finally documented for am335x?
Thanks,
Richard
WARNING: multiple messages have this Message-ID (diff)
From: Richard Cochran <richardcochran@gmail.com>
To: George Cherian <george.cherian@ti.com>
Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
linux-omap@vger.kernel.org, davem@davemloft.net,
jeffrey.t.kirsher@intel.com, dborkman@redhat.com,
ast@plumgrid.com, tklauser@distanz.ch, mpa@pengutronix.de,
bhutchings@solarflare.com, zonque@gmail.com, balbi@ti.com,
mugunthanvnm@ti.com, t-kristo@ti.com, mturquette@linaro.org,
linux@arm.linux.org.uk, galak@codeaurora.org,
ijc+devicetree@hellion.org.uk, mark.rutland@arm.com,
pawel.moll@arm.com, robh+dt@kernel.org, tony@atomide.com,
bcousson@baylibre.com
Subject: Re: [PATCH 4/6] drivers: net: cpsw: Enable Annexe F Time sync
Date: Mon, 28 Apr 2014 09:55:31 +0200 [thread overview]
Message-ID: <20140428075530.GA8371@netboy> (raw)
In-Reply-To: <1398658225-25873-5-git-send-email-george.cherian@ti.com>
On Mon, Apr 28, 2014 at 09:40:23AM +0530, George Cherian wrote:
> Enable the Annex F Time Sync explicitly for DRA7x and AM4372.
> With this enabled the L2 PTP is working.
L2 works fine without this bit. If this is needed for V3 hardware,
then it should have its own code variant.
> while at that rename TS_BIT8 to TS_TTL_NONZERO
Is this bit finally documented for am335x?
Thanks,
Richard
next prev parent reply other threads:[~2014-04-28 7:55 UTC|newest]
Thread overview: 51+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-04-28 4:10 [PATCH 0/6] Add CPTS support for AM437x George Cherian
2014-04-28 4:10 ` George Cherian
2014-04-28 4:10 ` George Cherian
2014-04-28 4:10 ` George Cherian
2014-04-28 4:10 ` [PATCH 1/6] drivers: net: cpts: Remove hardcoded clock name for CPTS George Cherian
2014-04-28 4:10 ` George Cherian
2014-04-28 4:10 ` George Cherian
[not found] ` <1398658225-25873-2-git-send-email-george.cherian-l0cyMroinI0@public.gmane.org>
2014-04-28 6:55 ` Richard Cochran
2014-04-28 6:55 ` Richard Cochran
2014-04-28 6:55 ` Richard Cochran
2014-04-28 14:31 ` Felipe Balbi
2014-04-28 14:31 ` Felipe Balbi
2014-04-28 14:31 ` Felipe Balbi
2014-04-28 14:45 ` George Cherian
2014-04-28 14:45 ` George Cherian
2014-04-28 14:45 ` George Cherian
2014-04-28 14:45 ` George Cherian
2014-04-28 4:10 ` [PATCH 2/6] ARM: dts: am33xx: Add clock names for cpsw and cpts George Cherian
2014-04-28 4:10 ` George Cherian
2014-04-28 4:10 ` George Cherian
2014-04-28 4:10 ` George Cherian
2014-04-28 4:10 ` [PATCH 3/6] drivers: net: cpsw: Enable CPTS for DRA7xx and AM4372 George Cherian
2014-04-28 4:10 ` George Cherian
2014-04-28 4:10 ` George Cherian
2014-04-28 4:10 ` [PATCH 4/6] drivers: net: cpsw: Enable Annexe F Time sync George Cherian
2014-04-28 4:10 ` George Cherian
2014-04-28 4:10 ` George Cherian
[not found] ` <1398658225-25873-5-git-send-email-george.cherian-l0cyMroinI0@public.gmane.org>
2014-04-28 7:55 ` Richard Cochran [this message]
2014-04-28 7:55 ` Richard Cochran
2014-04-28 7:55 ` Richard Cochran
2014-04-28 12:58 ` George Cherian
2014-04-28 12:58 ` George Cherian
2014-04-28 12:58 ` George Cherian
2014-04-28 4:10 ` [PATCH 5/6] ARM: AM43xx: clk: Change the cpts ref clock source to dpll_core_m5 clk George Cherian
2014-04-28 4:10 ` George Cherian
2014-04-28 4:10 ` George Cherian
2014-04-28 7:10 ` Richard Cochran
2014-04-28 7:10 ` Richard Cochran
2014-04-28 12:55 ` George Cherian
2014-04-28 12:55 ` George Cherian
2014-04-28 12:55 ` George Cherian
2014-04-28 16:18 ` Richard Cochran
2014-04-28 16:18 ` Richard Cochran
2014-04-29 4:28 ` George Cherian
2014-04-29 4:28 ` George Cherian
2014-04-29 4:28 ` George Cherian
2014-04-29 4:28 ` George Cherian
[not found] ` <1398658225-25873-1-git-send-email-george.cherian-l0cyMroinI0@public.gmane.org>
2014-04-28 4:10 ` [PATCH 6/6] ARM: dts: am4372: Add clock names for cpsw and cpts George Cherian
2014-04-28 4:10 ` George Cherian
2014-04-28 4:10 ` George Cherian
2014-04-28 4:10 ` George Cherian
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