* [PATCH v2] drm/i915: Rename defines for selection of ddi buffer translation slot @ 2014-08-08 12:17 sonika.jindal 2014-08-08 12:36 ` Damien Lespiau 0 siblings, 1 reply; 8+ messages in thread From: sonika.jindal @ 2014-08-08 12:17 UTC (permalink / raw) To: intel-gfx From: Sonika Jindal <sonika.jindal@intel.com> Renaming the HSW-specific macros for ddi buffer translation slot to denote the slot and not the vswing/pre-emph values as they are platform-dependent. This patch is based on top of the patch series for renaming the DP training vswing/pre-emph defines: http://lists.freedesktop.org/archives/intel-gfx/2014-August/050407.html v2: Creating single macro with argument for slot number (Damien) Signed-off-by: Sonika Jindal <sonika.jindal@intel.com> --- drivers/gpu/drm/i915/i915_reg.h | 10 +--------- drivers/gpu/drm/i915/intel_ddi.c | 19 +++---------------- drivers/gpu/drm/i915/intel_dp.c | 18 +++++++++--------- 3 files changed, 13 insertions(+), 34 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 7a6cc69..7366aac 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -5966,15 +5966,7 @@ enum punit_power_well { #define DDI_BUF_CTL_B 0x64100 #define DDI_BUF_CTL(port) _PORT(port, DDI_BUF_CTL_A, DDI_BUF_CTL_B) #define DDI_BUF_CTL_ENABLE (1<<31) -#define DDI_BUF_EMP_400MV_0DB_HSW (0<<24) /* Sel0 */ -#define DDI_BUF_EMP_400MV_3_5DB_HSW (1<<24) /* Sel1 */ -#define DDI_BUF_EMP_400MV_6DB_HSW (2<<24) /* Sel2 */ -#define DDI_BUF_EMP_400MV_9_5DB_HSW (3<<24) /* Sel3 */ -#define DDI_BUF_EMP_600MV_0DB_HSW (4<<24) /* Sel4 */ -#define DDI_BUF_EMP_600MV_3_5DB_HSW (5<<24) /* Sel5 */ -#define DDI_BUF_EMP_600MV_6DB_HSW (6<<24) /* Sel6 */ -#define DDI_BUF_EMP_800MV_0DB_HSW (7<<24) /* Sel7 */ -#define DDI_BUF_EMP_800MV_3_5DB_HSW (8<<24) /* Sel8 */ +#define DDI_BUF_TRANS_SELECT(n) ((n) << 24) #define DDI_BUF_EMP_MASK (0xf<<24) #define DDI_BUF_PORT_REVERSAL (1<<16) #define DDI_BUF_IS_IDLE (1<<7) diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index ca1f9a8..493cf3a 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -241,18 +241,6 @@ void intel_prepare_ddi(struct drm_device *dev) intel_prepare_ddi_buffers(dev, port); } -static const long hsw_ddi_buf_ctl_values[] = { - DDI_BUF_EMP_400MV_0DB_HSW, - DDI_BUF_EMP_400MV_3_5DB_HSW, - DDI_BUF_EMP_400MV_6DB_HSW, - DDI_BUF_EMP_400MV_9_5DB_HSW, - DDI_BUF_EMP_600MV_0DB_HSW, - DDI_BUF_EMP_600MV_3_5DB_HSW, - DDI_BUF_EMP_600MV_6DB_HSW, - DDI_BUF_EMP_800MV_0DB_HSW, - DDI_BUF_EMP_800MV_3_5DB_HSW -}; - static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, enum port port) { @@ -275,7 +263,6 @@ static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, * please note that when FDI mode is active on DDI E, it shares 2 lines with * DDI A (which is used for eDP) */ - void hsw_fdi_link_train(struct drm_crtc *crtc) { struct drm_device *dev = crtc->dev; @@ -312,7 +299,7 @@ void hsw_fdi_link_train(struct drm_crtc *crtc) /* Start the training iterating through available voltages and emphasis, * testing each value twice. */ - for (i = 0; i < ARRAY_SIZE(hsw_ddi_buf_ctl_values) * 2; i++) { + for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi); i++) { /* Configure DP_TP_CTL with auto-training */ I915_WRITE(DP_TP_CTL(PORT_E), DP_TP_CTL_FDI_AUTOTRAIN | @@ -327,7 +314,7 @@ void hsw_fdi_link_train(struct drm_crtc *crtc) I915_WRITE(DDI_BUF_CTL(PORT_E), DDI_BUF_CTL_ENABLE | ((intel_crtc->config.fdi_lanes - 1) << 1) | - hsw_ddi_buf_ctl_values[i / 2]); + DDI_BUF_TRANS_SELECT(i / 2)); POSTING_READ(DDI_BUF_CTL(PORT_E)); udelay(600); @@ -402,7 +389,7 @@ void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder) enc_to_dig_port(&encoder->base); intel_dp->DP = intel_dig_port->saved_port_bits | - DDI_BUF_CTL_ENABLE | DDI_BUF_EMP_400MV_0DB_HSW; + DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0); intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count); } diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 01f264c..7215cfe 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -2842,25 +2842,25 @@ intel_hsw_signal_levels(uint8_t train_set) DP_TRAIN_PRE_EMPHASIS_MASK); switch (signal_levels) { case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: - return DDI_BUF_EMP_400MV_0DB_HSW; + return DDI_BUF_TRANS_SELECT(0); case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: - return DDI_BUF_EMP_400MV_3_5DB_HSW; + return DDI_BUF_TRANS_SELECT(1); case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: - return DDI_BUF_EMP_400MV_6DB_HSW; + return DDI_BUF_TRANS_SELECT(2); case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3: - return DDI_BUF_EMP_400MV_9_5DB_HSW; + return DDI_BUF_TRANS_SELECT(3); case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: - return DDI_BUF_EMP_600MV_0DB_HSW; + return DDI_BUF_TRANS_SELECT(4); case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: - return DDI_BUF_EMP_600MV_3_5DB_HSW; + return DDI_BUF_TRANS_SELECT(5); case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2: - return DDI_BUF_EMP_600MV_6DB_HSW; + return DDI_BUF_TRANS_SELECT(6); case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: - return DDI_BUF_EMP_800MV_0DB_HSW; + return DDI_BUF_TRANS_SELECT(7); case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: - return DDI_BUF_EMP_800MV_3_5DB_HSW; + return DDI_BUF_TRANS_SELECT(8); default: DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" "0x%x\n", signal_levels); -- 1.7.10.4 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH v2] drm/i915: Rename defines for selection of ddi buffer translation slot 2014-08-08 12:17 [PATCH v2] drm/i915: Rename defines for selection of ddi buffer translation slot sonika.jindal @ 2014-08-08 12:36 ` Damien Lespiau 2014-08-27 11:16 ` Ville Syrjälä 0 siblings, 1 reply; 8+ messages in thread From: Damien Lespiau @ 2014-08-08 12:36 UTC (permalink / raw) To: sonika.jindal; +Cc: intel-gfx On Fri, Aug 08, 2014 at 05:47:25PM +0530, sonika.jindal@intel.com wrote: > /* Start the training iterating through available voltages and emphasis, > * testing each value twice. */ > - for (i = 0; i < ARRAY_SIZE(hsw_ddi_buf_ctl_values) * 2; i++) { > + for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi); i++) { This is correct but obsfucated. You're actually doing ARRAY_SIZE(hsw_ddi_translations_fdi) / 2 * 2 and we might as well give the ARRAY_SIZE(hsw_ddi_translations_fdi) / 2 a proper name like I suggested. With that fixed, you can add my: Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> -- Damien ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v2] drm/i915: Rename defines for selection of ddi buffer translation slot 2014-08-08 12:36 ` Damien Lespiau @ 2014-08-27 11:16 ` Ville Syrjälä 2014-08-27 11:26 ` Damien Lespiau 0 siblings, 1 reply; 8+ messages in thread From: Ville Syrjälä @ 2014-08-27 11:16 UTC (permalink / raw) To: Damien Lespiau; +Cc: intel-gfx On Fri, Aug 08, 2014 at 01:36:17PM +0100, Damien Lespiau wrote: > On Fri, Aug 08, 2014 at 05:47:25PM +0530, sonika.jindal@intel.com wrote: > > /* Start the training iterating through available voltages and emphasis, > > * testing each value twice. */ > > - for (i = 0; i < ARRAY_SIZE(hsw_ddi_buf_ctl_values) * 2; i++) { > > + for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi); i++) { > > This is correct but obsfucated. You're actually doing > ARRAY_SIZE(hsw_ddi_translations_fdi) / 2 * 2 and we might as well give > the ARRAY_SIZE(hsw_ddi_translations_fdi) / 2 a proper name like I > suggested. I've been wondering why we don't have something like: struct ddi_buf_trans { u32 deemp; u32 vswing; } and use that instead of having the magic /2 appear in places. -- Ville Syrjälä Intel OTC ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v2] drm/i915: Rename defines for selection of ddi buffer translation slot 2014-08-27 11:16 ` Ville Syrjälä @ 2014-08-27 11:26 ` Damien Lespiau 2014-08-27 13:27 ` [PATCH] drm/i915/ddi: use struct for ddi buf translation tables Jani Nikula 0 siblings, 1 reply; 8+ messages in thread From: Damien Lespiau @ 2014-08-27 11:26 UTC (permalink / raw) To: Ville Syrjälä; +Cc: intel-gfx On Wed, Aug 27, 2014 at 02:16:13PM +0300, Ville Syrjälä wrote: > On Fri, Aug 08, 2014 at 01:36:17PM +0100, Damien Lespiau wrote: > > On Fri, Aug 08, 2014 at 05:47:25PM +0530, sonika.jindal@intel.com wrote: > > > /* Start the training iterating through available voltages and emphasis, > > > * testing each value twice. */ > > > - for (i = 0; i < ARRAY_SIZE(hsw_ddi_buf_ctl_values) * 2; i++) { > > > + for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi); i++) { > > > > This is correct but obsfucated. You're actually doing > > ARRAY_SIZE(hsw_ddi_translations_fdi) / 2 * 2 and we might as well give > > the ARRAY_SIZE(hsw_ddi_translations_fdi) / 2 a proper name like I > > suggested. > > I've been wondering why we don't have something like: > > struct ddi_buf_trans { > u32 deemp; > u32 vswing; > } > > and use that instead of having the magic /2 appear in places. Yes, this is something we've discussed in a separate thread with Jani as well and that'd be indeed even better. Someone wants to sign up for that? -- Damien ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH] drm/i915/ddi: use struct for ddi buf translation tables 2014-08-27 11:26 ` Damien Lespiau @ 2014-08-27 13:27 ` Jani Nikula 2014-08-27 13:47 ` Damien Lespiau 2014-08-27 13:49 ` Daniel Vetter 0 siblings, 2 replies; 8+ messages in thread From: Jani Nikula @ 2014-08-27 13:27 UTC (permalink / raw) To: intel-gfx; +Cc: jani.nikula Try to avoid confusion with ARRAY_SIZE()/2 and hdmi_level*2. Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- This is on top of nightly; I can respin this on top of Sonika's patch after that gets merged. BR, Jani. --- drivers/gpu/drm/i915/intel_ddi.c | 181 ++++++++++++++++++++------------------- 1 file changed, 95 insertions(+), 86 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index 02d55843c78d..acfdb4b28910 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -28,98 +28,103 @@ #include "i915_drv.h" #include "intel_drv.h" +struct ddi_buf_trans { + u32 trans1; /* balance leg enable, de-emph level */ + u32 trans2; /* vref sel, vswing */ +}; + /* HDMI/DVI modes ignore everything but the last 2 items. So we share * them for both DP and FDI transports, allowing those ports to * automatically adapt to HDMI connections as well */ -static const u32 hsw_ddi_translations_dp[] = { - 0x00FFFFFF, 0x0006000E, - 0x00D75FFF, 0x0005000A, - 0x00C30FFF, 0x00040006, - 0x80AAAFFF, 0x000B0000, - 0x00FFFFFF, 0x0005000A, - 0x00D75FFF, 0x000C0004, - 0x80C30FFF, 0x000B0000, - 0x00FFFFFF, 0x00040006, - 0x80D75FFF, 0x000B0000, +static const struct ddi_buf_trans hsw_ddi_translations_dp[] = { + { 0x00FFFFFF, 0x0006000E }, + { 0x00D75FFF, 0x0005000A }, + { 0x00C30FFF, 0x00040006 }, + { 0x80AAAFFF, 0x000B0000 }, + { 0x00FFFFFF, 0x0005000A }, + { 0x00D75FFF, 0x000C0004 }, + { 0x80C30FFF, 0x000B0000 }, + { 0x00FFFFFF, 0x00040006 }, + { 0x80D75FFF, 0x000B0000 }, }; -static const u32 hsw_ddi_translations_fdi[] = { - 0x00FFFFFF, 0x0007000E, - 0x00D75FFF, 0x000F000A, - 0x00C30FFF, 0x00060006, - 0x00AAAFFF, 0x001E0000, - 0x00FFFFFF, 0x000F000A, - 0x00D75FFF, 0x00160004, - 0x00C30FFF, 0x001E0000, - 0x00FFFFFF, 0x00060006, - 0x00D75FFF, 0x001E0000, +static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = { + { 0x00FFFFFF, 0x0007000E }, + { 0x00D75FFF, 0x000F000A }, + { 0x00C30FFF, 0x00060006 }, + { 0x00AAAFFF, 0x001E0000 }, + { 0x00FFFFFF, 0x000F000A }, + { 0x00D75FFF, 0x00160004 }, + { 0x00C30FFF, 0x001E0000 }, + { 0x00FFFFFF, 0x00060006 }, + { 0x00D75FFF, 0x001E0000 }, }; -static const u32 hsw_ddi_translations_hdmi[] = { - /* Idx NT mV diff T mV diff db */ - 0x00FFFFFF, 0x0006000E, /* 0: 400 400 0 */ - 0x00E79FFF, 0x000E000C, /* 1: 400 500 2 */ - 0x00D75FFF, 0x0005000A, /* 2: 400 600 3.5 */ - 0x00FFFFFF, 0x0005000A, /* 3: 600 600 0 */ - 0x00E79FFF, 0x001D0007, /* 4: 600 750 2 */ - 0x00D75FFF, 0x000C0004, /* 5: 600 900 3.5 */ - 0x00FFFFFF, 0x00040006, /* 6: 800 800 0 */ - 0x80E79FFF, 0x00030002, /* 7: 800 1000 2 */ - 0x00FFFFFF, 0x00140005, /* 8: 850 850 0 */ - 0x00FFFFFF, 0x000C0004, /* 9: 900 900 0 */ - 0x00FFFFFF, 0x001C0003, /* 10: 950 950 0 */ - 0x80FFFFFF, 0x00030002, /* 11: 1000 1000 0 */ +static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = { + /* Idx NT mV d T mV d db */ + { 0x00FFFFFF, 0x0006000E }, /* 0: 400 400 0 */ + { 0x00E79FFF, 0x000E000C }, /* 1: 400 500 2 */ + { 0x00D75FFF, 0x0005000A }, /* 2: 400 600 3.5 */ + { 0x00FFFFFF, 0x0005000A }, /* 3: 600 600 0 */ + { 0x00E79FFF, 0x001D0007 }, /* 4: 600 750 2 */ + { 0x00D75FFF, 0x000C0004 }, /* 5: 600 900 3.5 */ + { 0x00FFFFFF, 0x00040006 }, /* 6: 800 800 0 */ + { 0x80E79FFF, 0x00030002 }, /* 7: 800 1000 2 */ + { 0x00FFFFFF, 0x00140005 }, /* 8: 850 850 0 */ + { 0x00FFFFFF, 0x000C0004 }, /* 9: 900 900 0 */ + { 0x00FFFFFF, 0x001C0003 }, /* 10: 950 950 0 */ + { 0x80FFFFFF, 0x00030002 }, /* 11: 1000 1000 0 */ }; -static const u32 bdw_ddi_translations_edp[] = { - 0x00FFFFFF, 0x00000012, - 0x00EBAFFF, 0x00020011, - 0x00C71FFF, 0x0006000F, - 0x00AAAFFF, 0x000E000A, - 0x00FFFFFF, 0x00020011, - 0x00DB6FFF, 0x0005000F, - 0x00BEEFFF, 0x000A000C, - 0x00FFFFFF, 0x0005000F, - 0x00DB6FFF, 0x000A000C, +static const struct ddi_buf_trans bdw_ddi_translations_edp[] = { + { 0x00FFFFFF, 0x00000012 }, + { 0x00EBAFFF, 0x00020011 }, + { 0x00C71FFF, 0x0006000F }, + { 0x00AAAFFF, 0x000E000A }, + { 0x00FFFFFF, 0x00020011 }, + { 0x00DB6FFF, 0x0005000F }, + { 0x00BEEFFF, 0x000A000C }, + { 0x00FFFFFF, 0x0005000F }, + { 0x00DB6FFF, 0x000A000C }, }; -static const u32 bdw_ddi_translations_dp[] = { - 0x00FFFFFF, 0x0007000E, - 0x00D75FFF, 0x000E000A, - 0x00BEFFFF, 0x00140006, - 0x80B2CFFF, 0x001B0002, - 0x00FFFFFF, 0x000E000A, - 0x00D75FFF, 0x00180004, - 0x80CB2FFF, 0x001B0002, - 0x00F7DFFF, 0x00180004, - 0x80D75FFF, 0x001B0002, +static const struct ddi_buf_trans bdw_ddi_translations_dp[] = { + { 0x00FFFFFF, 0x0007000E }, + { 0x00D75FFF, 0x000E000A }, + { 0x00BEFFFF, 0x00140006 }, + { 0x80B2CFFF, 0x001B0002 }, + { 0x00FFFFFF, 0x000E000A }, + { 0x00D75FFF, 0x00180004 }, + { 0x80CB2FFF, 0x001B0002 }, + { 0x00F7DFFF, 0x00180004 }, + { 0x80D75FFF, 0x001B0002 }, }; -static const u32 bdw_ddi_translations_fdi[] = { - 0x00FFFFFF, 0x0001000E, - 0x00D75FFF, 0x0004000A, - 0x00C30FFF, 0x00070006, - 0x00AAAFFF, 0x000C0000, - 0x00FFFFFF, 0x0004000A, - 0x00D75FFF, 0x00090004, - 0x00C30FFF, 0x000C0000, - 0x00FFFFFF, 0x00070006, - 0x00D75FFF, 0x000C0000, +static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = { + { 0x00FFFFFF, 0x0001000E }, + { 0x00D75FFF, 0x0004000A }, + { 0x00C30FFF, 0x00070006 }, + { 0x00AAAFFF, 0x000C0000 }, + { 0x00FFFFFF, 0x0004000A }, + { 0x00D75FFF, 0x00090004 }, + { 0x00C30FFF, 0x000C0000 }, + { 0x00FFFFFF, 0x00070006 }, + { 0x00D75FFF, 0x000C0000 }, }; -static const u32 bdw_ddi_translations_hdmi[] = { - /* Idx NT mV diff T mV diff db */ - 0x00FFFFFF, 0x0007000E, /* 0: 400 400 0 */ - 0x00D75FFF, 0x000E000A, /* 1: 400 600 3.5 */ - 0x00BEFFFF, 0x00140006, /* 2: 400 800 6 */ - 0x00FFFFFF, 0x0009000D, /* 3: 450 450 0 */ - 0x00FFFFFF, 0x000E000A, /* 4: 600 600 0 */ - 0x00D7FFFF, 0x00140006, /* 5: 600 800 2.5 */ - 0x80CB2FFF, 0x001B0002, /* 6: 600 1000 4.5 */ - 0x00FFFFFF, 0x00140006, /* 7: 800 800 0 */ - 0x80E79FFF, 0x001B0002, /* 8: 800 1000 2 */ - 0x80FFFFFF, 0x001B0002, /* 9: 1000 1000 0 */ +static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = { + /* Idx NT mV d T mV df db */ + { 0x00FFFFFF, 0x0007000E }, /* 0: 400 400 0 */ + { 0x00D75FFF, 0x000E000A }, /* 1: 400 600 3.5 */ + { 0x00BEFFFF, 0x00140006 }, /* 2: 400 800 6 */ + { 0x00FFFFFF, 0x0009000D }, /* 3: 450 450 0 */ + { 0x00FFFFFF, 0x000E000A }, /* 4: 600 600 0 */ + { 0x00D7FFFF, 0x00140006 }, /* 5: 600 800 2.5 */ + { 0x80CB2FFF, 0x001B0002 }, /* 6: 600 1000 4.5 */ + { 0x00FFFFFF, 0x00140006 }, /* 7: 800 800 0 */ + { 0x80E79FFF, 0x001B0002 }, /* 8: 800 1000 2 */ + { 0x80FFFFFF, 0x001B0002 }, /* 9: 1000 1000 0 */ }; enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder) @@ -158,25 +163,25 @@ static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port) u32 reg; int i, n_hdmi_entries, hdmi_800mV_0dB; int hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift; - const u32 *ddi_translations_fdi; - const u32 *ddi_translations_dp; - const u32 *ddi_translations_edp; - const u32 *ddi_translations_hdmi; - const u32 *ddi_translations; + const struct ddi_buf_trans *ddi_translations_fdi; + const struct ddi_buf_trans *ddi_translations_dp; + const struct ddi_buf_trans *ddi_translations_edp; + const struct ddi_buf_trans *ddi_translations_hdmi; + const struct ddi_buf_trans *ddi_translations; if (IS_BROADWELL(dev)) { ddi_translations_fdi = bdw_ddi_translations_fdi; ddi_translations_dp = bdw_ddi_translations_dp; ddi_translations_edp = bdw_ddi_translations_edp; ddi_translations_hdmi = bdw_ddi_translations_hdmi; - n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi) / 2; + n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi); hdmi_800mV_0dB = 7; } else if (IS_HASWELL(dev)) { ddi_translations_fdi = hsw_ddi_translations_fdi; ddi_translations_dp = hsw_ddi_translations_dp; ddi_translations_edp = hsw_ddi_translations_dp; ddi_translations_hdmi = hsw_ddi_translations_hdmi; - n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi) / 2; + n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi); hdmi_800mV_0dB = 6; } else { WARN(1, "ddi translation table missing\n"); @@ -184,7 +189,7 @@ static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port) ddi_translations_fdi = bdw_ddi_translations_fdi; ddi_translations_dp = bdw_ddi_translations_dp; ddi_translations_hdmi = bdw_ddi_translations_hdmi; - n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi) / 2; + n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi); hdmi_800mV_0dB = 7; } @@ -211,7 +216,9 @@ static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port) for (i = 0, reg = DDI_BUF_TRANS(port); i < ARRAY_SIZE(hsw_ddi_translations_fdi); i++) { - I915_WRITE(reg, ddi_translations[i]); + I915_WRITE(reg, ddi_translations[i].trans1); + reg += 4; + I915_WRITE(reg, ddi_translations[i].trans2); reg += 4; } @@ -222,7 +229,9 @@ static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port) /* Entry 9 is for HDMI: */ for (i = 0; i < 2; i++) { - I915_WRITE(reg, ddi_translations_hdmi[hdmi_level * 2 + i]); + I915_WRITE(reg, ddi_translations_hdmi[hdmi_level + i].trans1); + reg += 4; + I915_WRITE(reg, ddi_translations_hdmi[hdmi_level + i].trans2); reg += 4; } } -- 1.9.1 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH] drm/i915/ddi: use struct for ddi buf translation tables 2014-08-27 13:27 ` [PATCH] drm/i915/ddi: use struct for ddi buf translation tables Jani Nikula @ 2014-08-27 13:47 ` Damien Lespiau 2014-08-27 13:55 ` Daniel Vetter 2014-08-27 13:49 ` Daniel Vetter 1 sibling, 1 reply; 8+ messages in thread From: Damien Lespiau @ 2014-08-27 13:47 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-gfx On Wed, Aug 27, 2014 at 04:27:30PM +0300, Jani Nikula wrote: > /* Entry 9 is for HDMI: */ > for (i = 0; i < 2; i++) { > - I915_WRITE(reg, ddi_translations_hdmi[hdmi_level * 2 + i]); > + I915_WRITE(reg, ddi_translations_hdmi[hdmi_level + i].trans1); > + reg += 4; > + I915_WRITE(reg, ddi_translations_hdmi[hdmi_level + i].trans2); > reg += 4; > } It seems we're writing a bit too many times there now (we don't need the the for() loop anymore). -- Damien ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] drm/i915/ddi: use struct for ddi buf translation tables 2014-08-27 13:47 ` Damien Lespiau @ 2014-08-27 13:55 ` Daniel Vetter 0 siblings, 0 replies; 8+ messages in thread From: Daniel Vetter @ 2014-08-27 13:55 UTC (permalink / raw) To: Damien Lespiau; +Cc: Jani Nikula, intel-gfx On Wed, Aug 27, 2014 at 02:47:05PM +0100, Damien Lespiau wrote: > On Wed, Aug 27, 2014 at 04:27:30PM +0300, Jani Nikula wrote: > > /* Entry 9 is for HDMI: */ > > for (i = 0; i < 2; i++) { > > - I915_WRITE(reg, ddi_translations_hdmi[hdmi_level * 2 + i]); > > + I915_WRITE(reg, ddi_translations_hdmi[hdmi_level + i].trans1); > > + reg += 4; > > + I915_WRITE(reg, ddi_translations_hdmi[hdmi_level + i].trans2); > > reg += 4; > > } > > It seems we're writing a bit too many times there now (we don't need the > the for() loop anymore). It totally never happend ;-) Thanks, Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] drm/i915/ddi: use struct for ddi buf translation tables 2014-08-27 13:27 ` [PATCH] drm/i915/ddi: use struct for ddi buf translation tables Jani Nikula 2014-08-27 13:47 ` Damien Lespiau @ 2014-08-27 13:49 ` Daniel Vetter 1 sibling, 0 replies; 8+ messages in thread From: Daniel Vetter @ 2014-08-27 13:49 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-gfx On Wed, Aug 27, 2014 at 04:27:30PM +0300, Jani Nikula wrote: > Try to avoid confusion with ARRAY_SIZE()/2 and hdmi_level*2. > > Signed-off-by: Jani Nikula <jani.nikula@intel.com> > > --- > > This is on top of nightly; I can respin this on top of Sonika's patch > after that gets merged. Resolved myself since I've just shockingly noticed that I've totally not merged Sonika's patch and wanted to make good again ;-) Let's see how well that goes, queued for -next, thanks for the patch. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2014-08-27 13:54 UTC | newest] Thread overview: 8+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2014-08-08 12:17 [PATCH v2] drm/i915: Rename defines for selection of ddi buffer translation slot sonika.jindal 2014-08-08 12:36 ` Damien Lespiau 2014-08-27 11:16 ` Ville Syrjälä 2014-08-27 11:26 ` Damien Lespiau 2014-08-27 13:27 ` [PATCH] drm/i915/ddi: use struct for ddi buf translation tables Jani Nikula 2014-08-27 13:47 ` Damien Lespiau 2014-08-27 13:55 ` Daniel Vetter 2014-08-27 13:49 ` Daniel Vetter
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