From: will.deacon@arm.com (Will Deacon)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v5 3/3] kprobes: arm: enable OPTPROBES for ARM 32
Date: Thu, 4 Sep 2014 11:52:27 +0100 [thread overview]
Message-ID: <20140904105227.GC7156@arm.com> (raw)
In-Reply-To: <1409827235.3008.46.camel@linaro1.home>
On Thu, Sep 04, 2014 at 11:40:35AM +0100, Jon Medhurst (Tixy) wrote:
> On Wed, 2014-09-03 at 11:30 +0100, Will Deacon wrote:
> > On Wed, Sep 03, 2014 at 11:18:04AM +0100, Masami Hiramatsu wrote:
> > > (2014/09/02 22:49), Jon Medhurst (Tixy) wrote:
> > > > 1. On SMP systems it's very slow because of kprobe's use of stop_machine
> > > > for applying and removing probes, this forces the system to idle and
> > > > wait for the next scheduler tick for each probe change.
> > >
> > > Hmm, agreed. It seems that arm32 limitation of self-modifying code on SMP.
> > > I'm not sure how we can handle it, but I guess;
> > > - for some processors which have better coherent cache for SMP, we can
> > > atomically replace the breakpoint code with original code.
> >
> > Except that it's not an architected breakpoint instruction, as I mentioned
> > before. It's also not really a property of the cache.
> >
> > > - Even if we get an "undefined instruction" exception, its handler can
> > > ask kprobes if the address is under modifying or not. And if it is,
> > > we can just return from the exception to retry the execution.
> >
> > It's not as simple as that -- you could potentially see an interleaving of
> > the two instructions. The architecture is even broader than that:
> >
> > Concurrent modification and execution of instructions can lead to the
> > resulting instruction performing any behavior that can be achieved by
> > executing any sequence of instructions that can be executed from the
> > same Exception level,
> >
> > There are additional guarantees for some instructions (like the architected
> > BKPT instruction).
>
> I should point out that the current implementation of kprobes doesn't
> use stop_machine because it's trying to meet the above architecture
> restrictions, and that arming kprobes (changing probed instruction to an
> undefined instruction) isn't usually done under stop_machine, so other
> CPUs could be executing the original instruction as it's being modified.
>
> So, should we be making patch_text unconditionally use stop machine and
> remove all direct use of __patch_text? (E.g. by jump labels.)
You could take a look at what we do for arm64 (see aarch64_insn_hotpatch_safe)
for inspiration.
Will
WARNING: multiple messages have this Message-ID (diff)
From: Will Deacon <will.deacon@arm.com>
To: "Jon Medhurst (Tixy)" <tixy@linaro.org>
Cc: Masami Hiramatsu <masami.hiramatsu.pt@hitachi.com>,
Wang Nan <wangnan0@huawei.com>,
Russell King <linux@arm.linux.org.uk>,
"David A. Long" <dave.long@linaro.org>,
Taras Kondratiuk <taras.kondratiuk@linaro.org>,
Ben Dooks <ben.dooks@codethink.co.uk>,
Ananth N Mavinakayanahalli <ananth@in.ibm.com>,
Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>,
"David S. Miller" <davem@davemloft.net>,
Pei Feiyue <peifeiyue@huawei.com>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v5 3/3] kprobes: arm: enable OPTPROBES for ARM 32
Date: Thu, 4 Sep 2014 11:52:27 +0100 [thread overview]
Message-ID: <20140904105227.GC7156@arm.com> (raw)
In-Reply-To: <1409827235.3008.46.camel@linaro1.home>
On Thu, Sep 04, 2014 at 11:40:35AM +0100, Jon Medhurst (Tixy) wrote:
> On Wed, 2014-09-03 at 11:30 +0100, Will Deacon wrote:
> > On Wed, Sep 03, 2014 at 11:18:04AM +0100, Masami Hiramatsu wrote:
> > > (2014/09/02 22:49), Jon Medhurst (Tixy) wrote:
> > > > 1. On SMP systems it's very slow because of kprobe's use of stop_machine
> > > > for applying and removing probes, this forces the system to idle and
> > > > wait for the next scheduler tick for each probe change.
> > >
> > > Hmm, agreed. It seems that arm32 limitation of self-modifying code on SMP.
> > > I'm not sure how we can handle it, but I guess;
> > > - for some processors which have better coherent cache for SMP, we can
> > > atomically replace the breakpoint code with original code.
> >
> > Except that it's not an architected breakpoint instruction, as I mentioned
> > before. It's also not really a property of the cache.
> >
> > > - Even if we get an "undefined instruction" exception, its handler can
> > > ask kprobes if the address is under modifying or not. And if it is,
> > > we can just return from the exception to retry the execution.
> >
> > It's not as simple as that -- you could potentially see an interleaving of
> > the two instructions. The architecture is even broader than that:
> >
> > Concurrent modification and execution of instructions can lead to the
> > resulting instruction performing any behavior that can be achieved by
> > executing any sequence of instructions that can be executed from the
> > same Exception level,
> >
> > There are additional guarantees for some instructions (like the architected
> > BKPT instruction).
>
> I should point out that the current implementation of kprobes doesn't
> use stop_machine because it's trying to meet the above architecture
> restrictions, and that arming kprobes (changing probed instruction to an
> undefined instruction) isn't usually done under stop_machine, so other
> CPUs could be executing the original instruction as it's being modified.
>
> So, should we be making patch_text unconditionally use stop machine and
> remove all direct use of __patch_text? (E.g. by jump labels.)
You could take a look at what we do for arm64 (see aarch64_insn_hotpatch_safe)
for inspiration.
Will
next prev parent reply other threads:[~2014-09-04 10:52 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-08-27 13:02 [PATCH v5 0/3] kprobes: arm: enable OPTPROBES for ARM 32 Wang Nan
2014-08-27 13:02 ` Wang Nan
2014-08-27 13:02 ` [PATCH v5 1/3] ARM: probes: check stack operation when decoding Wang Nan
2014-08-27 13:02 ` Wang Nan
2014-08-28 9:51 ` Masami Hiramatsu
2014-08-28 9:51 ` Masami Hiramatsu
2014-08-28 10:20 ` Russell King - ARM Linux
2014-08-28 10:20 ` Russell King - ARM Linux
2014-08-28 10:24 ` Will Deacon
2014-08-28 10:24 ` Will Deacon
2014-08-29 8:47 ` Jon Medhurst (Tixy)
2014-08-29 8:47 ` Jon Medhurst (Tixy)
2014-08-30 1:28 ` Wang Nan
2014-08-30 1:28 ` Wang Nan
2014-09-01 17:29 ` Jon Medhurst (Tixy)
2014-09-01 17:29 ` Jon Medhurst (Tixy)
2014-08-27 13:02 ` [PATCH v5 2/3] kprobes: copy ainsn after alloc aggr kprobe Wang Nan
2014-08-27 13:02 ` Wang Nan
2014-08-28 9:39 ` Masami Hiramatsu
2014-08-28 9:39 ` Masami Hiramatsu
2014-08-28 11:07 ` Wang Nan
2014-08-28 11:07 ` Wang Nan
2014-08-27 13:02 ` [PATCH v5 3/3] kprobes: arm: enable OPTPROBES for ARM 32 Wang Nan
2014-08-27 13:02 ` Wang Nan
2014-08-28 10:20 ` Masami Hiramatsu
2014-08-28 10:20 ` Masami Hiramatsu
2014-09-02 13:49 ` Jon Medhurst (Tixy)
2014-09-02 13:49 ` Jon Medhurst (Tixy)
2014-09-03 10:18 ` Masami Hiramatsu
2014-09-03 10:18 ` Masami Hiramatsu
2014-09-03 10:30 ` Will Deacon
2014-09-03 10:30 ` Will Deacon
2014-09-04 10:40 ` Jon Medhurst (Tixy)
2014-09-04 10:40 ` Jon Medhurst (Tixy)
2014-09-04 10:52 ` Will Deacon [this message]
2014-09-04 10:52 ` Will Deacon
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20140904105227.GC7156@arm.com \
--to=will.deacon@arm.com \
--cc=linux-arm-kernel@lists.infradead.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.